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ADC34RF52 数据表(PDF) 13 Page - Texas Instruments |
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ADC34RF52 数据表(HTML) 13 Page - Texas Instruments |
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13 / 105 page  6.9 Timing Requirements (continued) Maximum and minimum values are specified over the operating free-air temperature range and nominal supply voltages. Typical values are specified at TA = 25°C, ADC sampling rate = 1.5 GSPS, Bypass mode, 50% clock duty cycle, AVDD18 = 1.8 V, AVDD12, CLKVDD, DVDD = 1.2 V, –1-dBFS differential input and dither DISABLED, unless otherwise noted PARAMETER TEST CONDITIONS MIN NOM MAX UNIT SERIAL PROGRAMMING INTERFACE (SCLK, SEN, SDIO) - Input fCLK(SCLK) Serial clock frequency 1 20 MHz tSU(SEN) SEN to rising edge of SCLK 10 ns tH(SEN) SEN from rising edge of SCLK 10 ns tSU(SDIO) SDIO to rising edge of SCLK 10 ns tH(SDIO) SDIO from rising edge of SCLK 10 ns SERIAL PROGRAMMING INTERFACE (SDIO) - Output t(OZD) SDIO tri-state to driven 10 ns t(ODZ) SDIO data to tri-state 14 ns t(OD) SDIO valid from falling edge of SCLK 10 ns TIMING: SYSREFP/M ts(SYSREF) Setup time, SYSREFP/M valid to rising edge of CLKP/M 50 ps th(SYSREF) Hold time, SYSREFP/M valid to rising edge of CLKP/M 50 ps CML SERDES OUTPUTS: DOUT[0..7]P/M fSerdes Serdes bit rate 0.5 12.8 13.0 Gbps RJ Random jitter, RMS RPAT, 6.4 Gbps 0.7 ps RJ Random jitter, RMS RPAT, 12.8 Gbps 0.6 ps DJ Deterministic jitter, peak to peak RPAT, 6.4 Gbps 8.9 ps DJ Deterministic jitter, peak to peak RPAT, 12.8 Gbps 14.7 ps TJ Total jitter, peak to peak RPAT, 6.4 Gbps 19.5 ps TJ Total jitter, peak to peak RPAT, 12.8 Gbps 24 www.ti.com ADC34RF52 SBASAI7 – MARCH 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: ADC34RF52 |
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