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HC705RC16GRS/D 数据表(PDF) 44 Page - NXP Semiconductors |
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HC705RC16GRS/D 数据表(HTML) 44 Page - NXP Semiconductors |
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44 / 120 page  Resets General Release Specification MC68HC705RC16 — Rev. 3.0 Resets 5.3 External Reset (RESET) The RESET pin is one of the two external sources of a reset. This pin is connected to a Schmitt trigger input gate to provide an upper and lower threshold voltage separated by a minimum amount of hysteresis. This external reset occurs whenever the RESET pin is pulled below the lower threshold and remains in reset until the RESET pin rises above the upper threshold. This active-low input will generate the RST signal and reset the CPU and peripherals. Termination of the external RESET input or the internal COP watchdog reset are the only reset sources that can alter the operating mode of the MCU. NOTE: Activation of the RST signal is generally referred to as reset of the device, unless otherwise specified. Figure 5-1. Reset Block Diagram CPU LATCH RESET COP WATCHDOG (COPR) RST OSC DATA ADDRESS PH2 TO OTHER PERIPHERALS S IRQ MODE SELECT TO IRQ LOGIC LATCH R POWER-ON RESET (POR) VDD ILLEGAL ADDRESS (ILLADDR) ADDRESS CLOCKED D D LPRST Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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