HC705V8GRSSLASHD datasheet(6/172 Pages) NXP

6 / 172 page

Page vii

MC68HC705V8 Specification Rev. 2.1

15.2.4

MDLC TX CONTROL REGISTER (MTCR) $10 ................106

15.2.5

MDLC RX STATUS REGISTER (MRSR) $11...................107

15.3

MDLC Rx/Tx BUFFERS .........................................................108

15.3.1

OUTLINE ...........................................................................108

15.3.2

RX BUFFERS....................................................................110

15.3.3

TX BUFFER ......................................................................111

15.4

MDLC PROTOCOL HANDLER ..............................................113

15.4.1

OUTLINE ...........................................................................113

15.4.2

Rx & Tx SHIFT REGISTERS ............................................114

15.4.3

STATE MACHINE .............................................................114

15.5

MDLC MUX INTERFACE .......................................................117

15.5.1

Rx DIGITAL FILTER..........................................................117

15.5.2

J1850 FRAME FORMAT ...................................................119

15.5.3

J1850 VPW SYMBOLS .....................................................121

15.5.4

J1850 VPW VALID/INVALID BITS & SYMBOLS ..............123

15.5.5

MESSAGE ARBITRATION ...............................................127

15.6

MDLC PHYSICAL INTERFACE .............................................129

15.6.1

OUTLINE ...........................................................................129

15.6.2

MUX INTERFACE SIGNALS ............................................131

15.6.3

PINS ..................................................................................132

15.7

MDLC APPLICATION NOTES ...............................................133

15.7.1

INITIALIZATION ................................................................133

15.7.2

TRANSMITTING A MESSAGE .........................................133

15.7.3

RECEIVING A MESSAGE ................................................133

15.7.4

RECEIVING A MESSAGE IN BLOCK MODE ...................134

15.7.5

MDLC STOP MODE..........................................................135

15.7.6

MDLC WAIT MODE ..........................................................135

15.7.7

CONTROLLING EXTERNAL VOLTAGE

REGULATORS................................................................135

SECTION 16

INSTRUCTION SET ..................................................... 137

16.1

16.2

READ-MODIFY-WRITE INSTRUCTIONS ..............................137

16.3

BRANCH INSTRUCTIONS.....................................................138

16.4

BIT MANIPULATION INSTRUCTIONS...................................138

16.5

CONTROL INSTRUCTIONS ..................................................139

16.6

ADDRESSING MODES ..........................................................139

16.6.1

IMMEDIATE ......................................................................140

16.6.2

DIRECT .............................................................................140

16.6.3

EXTENDED .......................................................................140

16.6.4

RELATIVE .........................................................................140

16.6.5

INDEXED, NO OFFSET ....................................................140

16.6.6

INDEXED, 8-BIT OFFSET ................................................140

16.6.7

INDEXED, 16-BIT OFFSET ..............................................141

16.6.8

BIT SET/CLEAR ................................................................141

16.6.9

BIT TEST AND BRANCH ..................................................141

16.6.10

INHERENT ........................................................................141

Freescale Semiconductor, Inc.

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