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QB-R5F100SL-TB 数据表(PDF) 38 Page - Renesas Technology Corp |
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QB-R5F100SL-TB 数据表(HTML) 38 Page - Renesas Technology Corp |
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38 / 207 page  RL78/G13 1. OUTLINE R01DS0131EJ0350 Rev.3.50 38 of 200 Jun 30, 2020 1.5.9 48-pin products PORT 1 P10 to P17 PORT 2 P20 to P27 8 PORT 3 P30, P31 2 PORT 4 PORT 5 8 PORT 12 P121 to P124 P40, P41 2 P50, P51 2 VOLTAGE REGULATOR REGC INTERRUPT CONTROL RAM WINDOW WATCHDOG TIMER POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RESET CONTROL SYSTEM CONTROL RESET X1/P121 X2/EXCLK/P122 HIGH-SPEED ON-CHIP OSCILLATOR ON-CHIP DEBUG TOOL0/P40 REAL-TIME CLOCK SERIAL ARRAY UNIT0 (4ch) UART0 RxD0/P11(RxD0/P16) TxD0/P12(TxD0/P17) UART1 RxD1/P01 TxD1/P00 SCL00/P10 SDA00/P11 IIC00 TIMER ARRAY UNIT (8ch) ch2 TI02/TO02/P17 (TI02/TO02/P15) ch3 TI03/TO03/P31 (TI03/TO03/P14) ch0 ch1 ch4 ch5 ch6 ch7 INTP8/P74, INTP9/P75 2 INTP0/P137 INTP3/P30, INTP4/P31 INTP6/P140 INTP1/P50, INTP2/P51 RxD2/P14 A/D CONVERTER 8 ANI0/P20 to ANI7/P27 AVREFP/P20 AVREFM/P21 4 P120 PORT 13 P130 P137 CSI11 SCK11/P30 SO11/P51 SI11/P50 SCL01/P75 SDA01/P74 IIC01 SCL11/P30 SDA11/P50 IIC11 TI07/TO07/P41 (TI07/TO07/P10) TI00/P00 TO00/P01 BCD ADJUSTMENT CSI00 SCK00/P10 SO00/P12 SI00/P11 VSS TOOLRxD/P11, TOOLTxD/P12 VDD SDAA0/P61(SDAA0/P13) SCLA0/P60(SCLA0/P14) SERIAL INTERFACE IICA0 2 2 INTP5/P16 MULTIPLIER& DIVIDER, MULTIPLY- ACCUMULATOR XT1/P123 XT2/EXCLKS/P124 PORT 0 P00, P01 2 BUZZER OUTPUT CLOCK OUTPUT CONTROL PCLBUZ0/P140 (PCLBUZ0/P31), PCLBUZ1/P15 KEY RETURN 6 KR0/P70 to KR5/P75 2 ANI18/P147, ANI19/P120 CSI01 SCK01/P75 SO01/P73 SI01/P74 SERIAL ARRAY UNIT1 (2ch) UART2 LINSEL RxD2/P14 TxD2/P13 SCL20/P15 SDA20/P14 IIC20 SCL21/P70 SDA21/P71 IIC21 CSI20 SCK20/P15 SO20/P13 SI20/P14 CSI21 SCK21/P70 SO21/P72 SI21/P71 DIRECT MEMORY ACCESS CONTROL PORT 6 PORT 7 P70 to P75 6 P60 to P63 4 PORT 14 P140, P146, P147 3 2 TI01/TO01/P16 RTC1HZ/P30 RxD2/P14 CODE FLASH MEMORY DATA FLASH MEMORY RL78 CPU CORE (TI04/TO04/P13) (TI05/TO05/P12) (TI06/TO06/P11) LOW-SPEED ON-CHIP OSCILLATOR 12- BIT INTERVAL TIMER CRC Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G13 User’s Manual. |
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