74LVC00APW datasheet(2/8 Pages) PHILIPS

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Philips Semiconductors

Product specification

74LVC00A

Quad 2-input NAND gate

1998 Apr 28

853-2017 19310

FEATURES

• Wide supply range of 1.2V to 3.6V

• Complies with JEDEC standard no. 8-1A

• Inputs accept voltages up to 5.5V

• CMOS low power consumption

• Direct interface with TTL levels

• 5-volt tolerant inputs, for interfacing with 5-volt logic

DESCRIPTION

The 74LVC00A is a high-performance, low power, low-voltage,

Si-gate CMOS device and superior to most advanced CMOS

compatible TTL families.

Inputs can be driven from either 3.3 V or 5 V devices. This feature

allows the use of these devices as translators in a mixed 3.3 V/5 V

environment.

Schmitt-trigger action at all inputs makes the circuit tolerant for

slower input rise and fall times.

The 74LVC00A provides the 2-input NAND function.

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25°C; tr =tf v2.5 ns

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

tPHL

tPLH

Propagation delay

nA, nB to nY

CL = 50 pF;

VCC = 3.3 V

3.0

Input capacitance

5.0

CPD

Power dissipation capacitance per gate

VI = GND to VCC1

NOTES:

1. CPD is used to determine the dynamic power dissipation (PD in µW)

PD = CPD

VCC2 x fi ) (CL

VCC2

fo) where:

fi = input frequency in MHz; CL = output load capacity in pF;

fo = output frequency in MHz; VCC = supply voltage in V;

(CL

VCC2

fo) = sum of the outputs.

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

OUTSIDE NORTH AMERICA

NORTH AMERICA

DWG NUMBER

14-Pin Plastic SO

–40

°C to +85°C

74LVC00A D

SOT108-1

14-Pin Plastic SSOP Type II

–40

°C to +85°C

74LVC00A DB

SOT337-1

14-Pin Plastic TSSOP Type I

–40

°C to +85°C

74LVC00A PW

74LVC00APW DH

SOT402-1

PIN CONFIGURATION

GND

VCC

SY00034

LOGIC SYMBOL (IEEE/IEC)

SV00378

LOGIC SYMBOL

SY00035

PIN DESCRIPTION

NUMBER

SYMBOL

NAME AND FUNCTION

1, 4, 9, 12

1A – 4A

Data inputs

2, 5, 10, 13

1B – 4B

Data inputs

3, 6, 8, 11

1Y – 4Y

Data outputs

GND

Ground (0 V)

VCC

Positive supply voltage

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