500mV to 5.5V Input nanoPower

Boost Converter with Short-Circuit

Protection

and True Shutdown

MAX18000

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Analog Devices | 15

Input Capacitor Selection

or most applications, bypass the I pin with a 10 22μ nominal ceramic input capacitors (CIN) that maintain 5μ or

higher effective capacitance at its working voltage. Effective CIN is the actual capacitance value seen from the converter

input during operation. Larger values improve decoupling for the converter but increase the inrush current from the voltage

supply when connected. CIN reduces the current peaks drawn from the input power source and reduces switching noise

in the system. The ESR/ESL of CIN and its series C trace should be very low (i.e., < 15mΩ + < 2nH) for frequencies

up to the converter's switching frequency.

Pay special attention to the capacitor's voltage rating, initial tolerance, variation with temperature, and DC bias

characteristic when selecting the CIN. Ceramic capacitors with X7R dielectrics are highly recommended due to their small

size, low ESR, and small temperature coefficients. All ceramic capacitors derate with DC bias voltage (effective

capacitance goes down as DC bias goes up). Generally, smaller case-size capacitors derate more heavily compared to

larger case sizes (0603 case size performs better than 0402). Consider the effective capacitance value carefully by

consulting the manufacturer's data sheet. Refer to Tutorial 5527 for more information.

Output Capacitor Selection

Sufficient output capacitance (COUT) is required for the stable operation of the converter. For minimum effective output

capacitances for different output voltage targets are shown in Table 2. Effective COUT is the actual capacitance value

seen by the converter output during operation. Larger values (above the required effective minimum) improve load

transient performance but increase input surge currents during soft-start and output voltage changes. The output filter

capacitor must have a low enough ESR for frequencies up to the converter's switching frequency to meet output ripple

and load transient requirements. The output capacitance must be high enough to absorb the inductor energy while

transitioning from full-load to no-load conditions. or most applications, 2 x 22μ capacitors (10 DC) are recommended

for COUT.

Pay special attention to the capacitor's voltage rating, initial tolerance, variation with temperature, and DC bias

characteristic when selecting COUT. Ceramic capacitors with X7R dielectrics are highly recommended due to their small

size, low ESR, and small temperature coefficients. All ceramic capacitors derate with DC bias voltage (effective

capacitance goes down as DC bias goes up). Generally, smaller case-size capacitors derate more heavily compared to

larger case sizes (0603 case size performs better than 0402). Consider the effective capacitance value carefully by

consulting the manufacturer's data sheet. Refer to Tutorial 5527 for more information.

Other Required Component Selection

The resistor between the RSEL pins and GND should have a tolerance of ±1% for the internal ADC to read the value

accurately.

PCB Layout Guideline

Careful circuit board layout is critical to achieve low switching power loss and clean, stable operation.

Use the following guidelines when designing the PCB:

• Place the input capacitors (CIN) and output capacitors (COUT) immediately next to the IN pin and OUT pin of the IC,

respectively. Since the IC operates at a high switching frequency with fast LX edges, this placement is critical for

minimizing parasitic inductance within the input and output current loops, which can cause high voltage spikes and

damage the internal switching MOSFETs.

• Place the inductor next to the LX bumps (as close as possible) and make the traces between the LX bumps and the

inductor short and wide to minimize PCB trace impedance. Excessive PCB impedance reduces converter efficiency.

When routing LX traces on a separate layer, make sure to include enough vias to minimize trace

impedance. Routing LX traces on multiple layers is recommended to further reduce trace impedance. Furthermore,

do not make LX traces take up an excessive amount of area. The voltage on this node switches very quickly, and

an additional area creates more radiated emissions.

• Connect the inner GND bumps to the low-impedance ground plane on the PCB with vias placed next to the bumps.

Do not create GND islands, as they risk interrupting the hot loops.

• Keep the power traces and load connections short and wide. This is essential for high converter efficiency.

• Do not neglect ceramic capacitor DC voltage derating. Choose capacitor values and case sizes carefully. See the

Output Capacitor Selection section and refer to Tutorial 5527 for more information.