Q5Q3ARCH-RMSLASHD datasheet(99/114 Pages) NXP

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Q5Q3ARCH-RM/D 数据表(PDF) 99 Page - NXP Semiconductors

部件名	Q5Q3ARCH-RM/D

功能描述	C-5e NETWORK PROCESSOR SILICON REVISION A1

PDF	114 Pages

Scroll/Zoom	100%

制造商	NXP [NXP Semiconductors]

网页	http://www.nxp.com

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AC Timing Specifications

QMU SRAM (Internal

Mode) Timing

Specifications

The QMU SRAM (Internal Mode) timing specifications are shown in Figure 26 and

described in Table 57.

Figure 26 QMU SRAM (Internal Mode) Timing Diagram

Data (TDn)

TD0 - TD63, TPAR0-3

Table 56 Signal Groups in TLU Timing Diagrams

SIGNAL GROUP

INCLUDED SIGNALS

QACLKI

Cycle 1

Cycle 2

Cycle 3

Cycle 4

Cycle 5

Q_ctl

QAn

QDn

(output)

QDn

(input)

Tqc

Tqdo

Tqco

Tqao

Tqdv

Tqds

Tqdz

Tqdh

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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