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PUMB2 数据表(PDF) 3 Page - Nexperia B.V. All rights reserved |
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PUMB2 数据表(HTML) 3 Page - Nexperia B.V. All rights reserved |
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3 / 14 page ![]() PEMB2_PUMB2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 17 November 2011 3 of 14 NXP Semiconductors PEMB2; PUMB2 PNP/PNP resistor-equipped transistors; R1 = 47 k , R2 = 47 k 5. Limiting values [1] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard footprint. [2] Reflow soldering is the only recommended soldering method. Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit Per transistor VCBO collector-base voltage open emitter - 50 V VCEO collector-emitter voltage open base - 50 V VEBO emitter-base voltage open collector - 10 V VI input voltage positive - +10 V negative - 40 V IO output current - 100 mA ICM peak collector current single pulse; tp 1ms - 100 mA Ptot total power dissipation Tamb 25 C PEMB2 (SOT666) [1][2] -200 mW PUMB2 (SOT363) [1] -200 mW Per device Ptot total power dissipation Tamb 25 C PEMB2 (SOT666) [1][2] -300 mW PUMB2 (SOT363) [1] -300 mW Tj junction temperature - 150 C Tamb ambient temperature 65 +150 C Tstg storage temperature 65 +150 C |
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