Philips Semiconductors

P89LPC920/921/922/9221

8-bit microcontrollers with two-clock 80C51 core

Product data

Rev. 08 — 15 December 2004

39 of 46

9397 750 14469

© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

[1]

Parameters are valid over operating temperature range unless otherwise specified. Parts are tested to 2 MHz, but are guaranteed to

operate down to 0 Hz.

[2]

When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to

hold the device in reset at power-up until VDD has reached its specified level. When system power is removed VDD will fall below the

minimum specified operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout

detect circuit may be required to hold the device in reset when VDD falls below the minimum specified operating voltage.

Table 10:

AC characteristics

VDD = 3.0 V to 3.6 V unless otherwise specified.

Tamb = −40 °Cto+85 °C for industrial, unless otherwise specified.[1]

Symbol

Parameter

Conditions

Variable clock

fosc =18MHz

Unit

Min

Max

Min

Max

fRCOSC

internal RC oscillator frequency

(nominal f = 7.3728 MHz)

trimmed to

±1%

at Tamb =25 °C

7.189

7.557

7.189

7.557

MHz

fWDOSC

internal Watchdog oscillator

frequency (nominal f = 400 kHz)

320

520

320

520

kHz

fosc

oscillator frequency

[2] 0

18

-

-

MHz

tCLCL

clock cycle

see Figure 13

55

-

-

-

ns

fCLKP

CLKLP active frequency

0

8

-

-

MHz

Glitch filter

glitch rejection, P1.5/RST pin

-

50

-

50

ns

signal acceptance, P1.5/RST pin

125

-

125

-

ns

glitch rejection, any pin except

P1.5/RST

-

15

-

15

ns

signal acceptance, any pin except

P1.5/RST

50

-

50

-

ns

External clock

tCHCX

HIGH time

see Figure 13

22

tCLCL − tCLCX

22

-

ns

tCLCX

LOW time

see Figure 13

22

tCLCL − tCHCX

22

-

ns

tCLCH

rise time

see Figure 13

-5

-

5

ns

tCHCL

fall time

see Figure 13

-5

-

5

ns

Shift register (UART mode 0)

tXLXL

serial port clock cycle time

16 tCLCL

-

888

-

ns

tQVXH

output data set-up to clock rising

edge

13 tCLCL

-

722

-

ns

tXHQX

output data hold after clock rising

edge

-tCLCL + 20

-

75

ns

tXHDX

input data hold after clock rising edge

-

0

-

0

ns

tDVXH

input data valid to clock rising edge

150

-

150

-

ns