DS0128 datasheet(49/140 Pages) MICROSEMI

49 / 140 page

IGLOO2 FPGA and SmartFusion2 SoC FPGA

Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0

Table 82 •

LVCMOS 1.2 V Receiver Characteristics for MSIOD I/O Bank (Input Buffers)

On-Die Termination (ODT)

TPY

TPYS

Unit

–1

–Std

–1

–Std

None

4.154

4.887

4.114

4.84

6.918

8.139

6.806

8.008

5.613

6.603

5.533

6.509

150

4.716

5.549

4.657

5.479

Table 83 •

LVCMOS 1.2 V Transmitter Characteristics for DDRIO I/O Bank (Output and Tristate Buffers)

Output

Drive

Selection

Slew

Control

TDP

TZL

TZH

THZ1

TLZ1

Unit

–1

–Std

–1

–Std

–1

–Std

–1

–Std

–1

–Std

2 mA

Slow

6.713

7.897

5.362 6.308

6.723

7.909

7.233

8.51

6.375

7.499

Medium

5.912

6.955

4.616 5.43

5.915

6.959

6.887

8.102

6.009

7.069

Medium

fast

5.5

6.469

4.231 4.978

5.5

6.471

6.672

7.849

5.835

6.865

Fast

5.462

6.426

4.194 4.935

5.463

6.427

6.646

7.819

5.828

6.857

4 mA

Slow

6.109

7.186

4.708 5.539

6.098

7.174

8.005

9.418

7.033

8.274

Medium

5.355

6.299

4.034 4.746

5.338

6.28

7.637

8.985

6.672

7.849

Medium

fast

4.953

5.826

3.685 4.336

4.932

5.802

7.44

8.752

6.499

7.646

Fast

4.911

5.777

3.658 4.303

4.89

5.754

7.427

8.737

6.488

7.632

6 mA

Slow

5.89

6.929

4.506 5.301

5.874

6.911

8.337

9.808

7.315

8.605

Medium

5.176

6.089

3.862 4.543

5.155

6.065

7.986

9.394

6.943

8.168

Medium

fast

4.792

5.637

3.523 4.145

4.765

5.606

7.808

9.186

6.775

7.97

Fast

4.754

5.593

3.486 4.101

4.728

5.563

7.777

9.149

6.769

7.963

Delay increases with drive strength are inherent to built-in slew control circuitry for simultaneous switching output (SSO)

management.

Table 84 •

LVCMOS 1.2 V Transmitter Characteristics for MSIO I/O Bank (Output and Tristate Buffers)

Output

Drive

Selection

Slew

Control

TDP

TZL

TZH

THZ1

TLZ1

Unit

–1

–Std

–1

–Std

–1

–Std

–1

–Std

–1

–Std

2 mA

Slow

6.746

7.937 7.458

8.774

8.172

9.614

9.867 11.608

8.393

9.874 ns

4 mA

Slow

7.068

8.315 6.678

7.857

7.474

8.793 10.986 12.924

9.043

10.638 ns

Delay increases with drive strength are inherent to built-in slew control circuitry for simultaneous switching output (SSO)

management.

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