M48T08 datasheet(9/27 Pages) STMICROELECTRONICS

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M48T08, M48T08Y, M48T18

WRITE Mode

The M48T08/18/08Y is in the WRITE Mode when-

ever W, E1, and E2 are active. The start of a

WRITE is referenced from the latter occurring fall-

ing edge of W or E1, or the rising edge of E2. A

WRITE is terminated by the earlier rising edge of

W or E1, or the falling edge of E2. The addresses

must be held valid throughout the cycle. E1 or W

must return high or E2 low for a minimum of tE1HAX

or tE2LAX from Chip Enable or tWHAX from WRITE

Enable prior to the initiation of another READ or

WRITE Cycle. Data-in must be valid tDVWH prior to

the end of WRITE and remain valid for tWHDX af-

terward. G should be kept high during WRITE Cy-

cles to avoid bus contention; however, if the output

bus has been activated by a low on E1 and G and

a high on E2, a low on W will disable the outputs

tWLQZ after W falls.

Figure 8. WRITE Enable Controlled, WRITE AC Waveform

AI00963

tAVAV

tWHAX

tDVWH

DATA INPUT

A0-A12

DQ0-DQ7

VALID

tAVWH

tAVE1L

tAVE2H

tWLWH

tAVWL

tWLQZ

tWHDX

tWHQX

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