Figure 37. Capacitive load response at Vcc = 3.3 V with a step of 100 mV

-40µ

-20µ

0

20µ

40µ

60µ

80µ

100µ

120µ

140µ

-100

-80

-60

-40

-20

0

20

40

60

80

100

-800

-700

-600

-500

-400

-300

-200

-100

0

100

200

300

400

500

600

700

800

Time (s)

Sample and hold

Vout

Vcc = 3.3 V, Vicm = 1.65V, Vsense = 0Vpp

T = 25°C,

5 kHz square signal of 100mV amplitude

injected in the output through 47pF

The effect of the ADC sampling and hold can be easily smoothed thanks to an RC filter. As suggested in the

schematic below in Figure 38. The capacitor of the external filter much be chosen much higher than the internal

ADC capacitor, in order to easily absorb the sudden voltage variation on the output due to the sampling and hold

of the ADC. And the resistance must be chosen according to the application speed of the system in order not to

impact the whole application. The main advantage to using an RC filter is to have an anti-aliasing system. The

ADC used must certainly have sample and hold conversion in accordance with the RC filter value, in order to let

the output recover before sampling.

Figure 38. RC filter when driving ADC

TSC21x

Vcc

+

-

Vref

Ct

10nF

100nF

ADC

Rs

In Figure 39 below an Rs = 1.3 kΩ resistance and a Ct = 470 pF capacitance have been set. Given a low pass

filter of 260 kHz and a response time of roughly 1.8 µs.

In Figure 40 below an Rs = 1.3 kΩ resistance and a Ct = 470 pF capacitance have been set. A load resistance of

10 kΩ is added in parallel of the Ct capacitance

TSC210, TSC211, TSC212, TSC213, TSC214, TSC215

Stability

DS13237 - Rev 6

page 20/38