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ICS9LPRS477C 数据表(PDF) 13 Page - Renesas Technology Corp |
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ICS9LPRS477C 数据表(HTML) 13 Page - Renesas Technology Corp |
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13 / 25 page  IDT® Programmable System Clock Chip for ATI RD790-K8TM Based Systems 1393—01/28/14 9LPRS477C Programmable System Clock Chip for ATI RD790 - K8TM based Systems 13 SMBus Table: CPU PLL Frequency Control Register Byte 17 Name Control Function Type 0 1 Default Bit 7 N Div10 RW X Bit 6 N Div9 RW X Bit 5 N Div8 RW X Bit 4 N Div7 RW X Bit 3 N Div6 RW X Bit 2 N Div5 RW X Bit 1 N Div4 RW X Bit 0 N Div3 RW X SMBus Table: SB_SRC PLL Spread Spectrum Control Register Byte 18 Name Control Function Type 0 1 Default Bit 7 SSP7 RW X Bit 6 SSP6 RW X Bit 5 SSP5 RW X Bit 4 SSP4 RW X Bit 3 SSP3 RW X Bit 2 SSP2 RW X Bit 1 SSP1 RW X Bit 0 SSP0 RW X SMBus Table: SB_SRC PLL Spread Spectrum Control Register Byte 19 Name Control Function Type 0 1 Default Bit 7 SSP15 RW X Bit 6 SSP14 RW X Bit 5 SSP13 RW X Bit 4 SSP12 RW X Bit 3 SSP11 RW X Bit 2 SSP10 RW X Bit 1 SSP9 RW X Bit 0 SSP8 RW X SMBUS Table: CPU Output Divider Register Byte 20 Name Control Function Type 0 1 Default Bit 7 CPU NDiv0 LSB N Divider Programming RW X Bit 6 X Bit 5 X Bit 4 X Bit 3 CPUDiv3 RW 0000:/2 ; 0100:/4 1000:/8 ; 1100:/16 X Bit 2 CPUDiv2 RW 0001:/3 ; 0101:/6 1001:/12 ; 1101:/24 X Bit 1 CPUDiv1 RW 0010:/5 ; 0110:/10 1010:/20 ; 1110:/40 X Bit 0 CPUDiv0 RW 0011:/9 ; 0111:/18 1011:/36 ; 1111:/72 X SMBUS Table: SRC Frequency Control Register Byte 21 Name Control Function Type 0 1 Default Bit 7 N Div2 N Divider Prog bit 2 RW X Bit 6 N Div1 N Divider Prog bit 1 RW X Bit 5 M Div5 RW X Bit 4 M Div4 RW X Bit 3 M Div3 RW X Bit 2 M Div2 RW X Bit 1 M Div1 RW X Bit 0 M Div0 RW X SMBUS Table: SRC Frequency Control Register Byte 22 Name Control Function Type 0 1 Default Bit 7 N Div10 RW X Bit 6 N Div9 RW X Bit 5 N Div8 RW X Bit 4 N Div7 RW X Bit 3 N Div6 RW X Bit 2 N Div5 RW X Bit 1 N Div4 RW X Bit 0 N Div3 RW X Reserved N Divider Programming Byte16 bit(7:0) and Byte15 bit(7:6) The decimal representation of M and N Divider in Byte 16 and 17 w ill configure the VCO frequency. Default at pow er up = Byte 3 Rom table. See M/N Caculation Tables for VCO frequency formulas. M Divider Programming bit (5:0) The decimal representation of M and N Divider in Byte 21 and 22 configure the SRC VCO frequency. See M/N Caculation Tables for VCO frequency formulas. Byte 28 has the N Divider LSB (bit 0) for CPU M/N programming. CPU Divider Ratio Programming Bits The decimal representation of M and N Divider in Byte 21 and 22 configure the SRC VCO frequency. See M/N Caculation Tables for VCO frequency formulas. N Divider Programming b(10:3) These bits set the SB_SRC spread pecentage.Please contact IDT for the appropriate values. Spread Spectrum Programming b(7:0) Spread Spectrum Programming b(15:8) These bits set the SB_SRC spread pecentage.Please contact IDT for the appropriate values. Reserved Reserved |
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