9LPRS477D

PROGRAMMABLE SYSTEM CLOCK CHIP FOR ATI RD790-K8TM BASED SYSTEMS

IDT®

PROGRAMMABLE SYSTEM CLOCK CHIP FOR ATI RD790-K8TM BASED SYSTEMS

21

9LPRS477D

REV C 010715

Clock Jitter Specifications–Low Power Differential Outputs

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS NOTES

t

jp ha sePLL

PCIe Gen 1

86

ps (p-p)

1,2

t

jp ha seLo

PCIe Gen 2

10kHz < f < 1.5MHz

3

ps

(RMS)

1,4

t

j pha seH igh

PCIe Gen 2

1.5MHz < f < Nyquist (50MHz)

3.1

ps

(RMS)

1,4

*TA = 0 - 70°C; S upply Voltage VDD = 3.3V +/-5%, Rs = 0ohms, CL = 2pF

4See http://www.pcisig.com for complete specs

SRC/SB_SRC/ATIG

Phase Jitter

1 Unless otherwise noted, guaranteed by design and characterization, not 100% tested in production.

2JItter specs are specified as measured on a clock characterization board. System designers need to take special care not to use these

numbers, as the in-system performance will be somewhat degraded. The receiver EMTS (chi spet or CPU) will have the rece

3 Phase jitter requirement: The deisgnated Gen2 outputs will meet the reference clock jitter requiremernts from the PCI Express Gen2 Base

Spec. The test is performed on a componnet test board under quiet condittions with all outputs on.