11

©2020 Renesas Electronics Corporation

February 19, 2020

9SQL4952/9SQL4954/9SQL4958 Datasheet

5 Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this

measurement.

6 Defines as the absolute minimum or maximum instantaneous period. This includes cycle to cycle jitter, relative ppm tolerance, and spread spectrum

modulation.

7 Defined as the maximum instantaneous voltage including overshoot.

8 Defined as the minimum instantaneous voltage including undershoot.

9 Defined as the total variation of all crossing voltages of Rising REFCLK+ and Falling REFCLK-. This is the maximum allowed variance in VCROSS

for any particular system.

10 Refer to Section 8.6.2 of the PCI Express Base Specification, Revision 5.0 for information regarding PPM considerations.

11 System board compliance measurements must use the test load. REFCLK+ and REFCLK- are to be measured at the load capacitors CL.

Single-ended probes must be used for measurements requiring single ended measurements. Either single-ended probes with math or differential

probe can be used for differential measurements. Test load CL = 2pF.

12 PCIe Gen1 through Gen4 specify ±300ppm frequency tolerances. PCIe Gen5 reduces the allowable tolerance to ±100ppm without spread

spectrum.

13 “ppm” refers to parts per million and is a DC absolute period accuracy specification. 1ppm is 1/1,000,000th of 100.000000MHz exactly or 100Hz.

For 100ppm, then we have an error budget of 100Hz/ppm × 100ppm = 10kHz. The period is to be measured with a frequency counter with

measurement window set to 100ms or greater. The ±100ppm applies to systems that do not employ Spread Spectrum clocking, or that use

common clock source. For systems employing Spread Spectrum clocking, there is an additional 2,500ppm nominal shift in maximum period

resulting from the 0.5% down spread resulting in a maximum average period specification of +2,600ppm for Common Clock architectures.

Separate Reference Clock architectures may have a lower allowed spread percentage.

14 Matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It is measured using a ±75 mV window centered on the

median cross point where REFCLK+ rising meets REFCLK- falling. The median cross point is used to calculate the voltage thresholds the

oscilloscope is to use for the edge rate calculations. The Rise Edge Rate of REFCLK+ should be compared to the Fall Edge Rate of REFCLK-;

the maximum allowed difference should not exceed 20% of the slowest edge rate.

15 At default SMBus amplitude settings.

1 Applies to all differential outputs, guaranteed by design and characterization. See Test Loads for measurement setup details.

2 Calculated from Intel™-supplied Clock Jitter Tool. Equipment noise removed from the results.

Table 8. UPI Phase Jitter of Differential Outputs

Parameter

Symbol

Conditions

Minimum

Typical

Maximum

Specification

Limits

Units

Notes

Phase Jitter, ZDB Mode tjphQPI_UPI

QPI and UPI

(100MHz, 8.0Gb/s, 12UI)

0.08

0.12

0.3

ps (RMS)

1,2

QPI and UPI

(100MHz, ≤11.4Gb/s, 12UI)

0.07

0.10

0.2

ps (RMS)

1,2

Table 9. 12kHz–20MHz Phase Jitter of Differential Outputs

Parameter

Symbol

Conditions

Minimum

Typical

Maximum

Units

Phase Jitter, 12kHz–20MHz tjph12k20M

Differential outputs when device is set to PCIe

SRnS mode (Byte1[4:3] = 00).

1.9

2

ps (rms)