9

©2020 Renesas Electronics Corporation

February 19, 2020

9SQL4952/9SQL4954/9SQL4958 Datasheet

Electrical Characteristics

TA = TAMB. Supply voltages per normal operation conditions; see Test Loads for loading conditions.

1 Guaranteed by design and characterization, not 100% tested in production.

2 The device must be powered up for the SMBus to function.

Table 5. SMBus Parameters

Parameter

Symbol

Conditions

Minimum

Typical

Maximum

Units Notes

SMBus Input Low Voltage

VILSMB

VDDSMB = 3.3V.

0.8

V

SMBus Input High Voltage

VIHSMB VDDSMB = 3.3V.

2.1

3.6

V

SMBus Output Low Voltage

VOLSMB At IPULLUP.

0.4

V

SMBus Sink Current

IPULLUP At VOL.

4mA

Nominal Bus Voltage

VDDSMB

2.7

3.6

V

SCLK/SDATA Rise Time

tRSMB

(Max. VIL - 0.15V) to (Min. VIH + 0.15V).

1000

ns

1

SCLK/SDATA Fall Time

tFSMB

(Min. VIH + 0.15V) to (Max. VIL - 0.15V).

300

ns

1

SMBus Operating Frequency

fSMB

SMBus operating frequency.

500

kHz

2

Table 6. Input/Supply/Common Parameters – Normal Operating Conditions

Parameter

Symbol

Conditions

Minimum

Typical

Maximum

Units

Notes

Supply Voltage

VDDxxx

Supply voltage for core, analog and single-ended

LVCMOS outputs.

3.135

3.3

3.465

V

IO Supply Voltage

VDDIO Supply voltage for differential low power outputs.

0.9975

1.05–3.3

3.465

V

Ambient Operating

Temperature

TAMB Industrial range.

-40

25

85

°C

Input High Voltage

VIH

Single-ended inputs, except SMBus.

0.75 x VDDx

VDDx + 0.3

V

Input Low Voltage

VIL

-0.3

0.25 x VDDx

V

Input High Voltage

VIHtri

Single-ended tri-level inputs

('_tri' suffix).

0.8 x VDDx

VDDx + 0.3

V

Input Mid Voltage

VIMtri

0.4 x VDDx 0.5 x VDDx

0.6 x VDDx

V

Input Low Voltage

VILtri

-0.3

0.20 x VDDx

V

Input Current

IIN

Single-ended inputs, VIN = GND, VIN = VDD.

-5

-0.05

5

μA

IINP

Single-ended inputs.

VIN = 0V; inputs with internal pull-up resistors.

VIN = VDD; inputs with internal pull-down

resistors.

-50

7

50

μA

Input Frequency

FIN

XTAL or X1 input.

25

MHz

4

Pin Inductance

Lpin

7nH

1

Capacitance

CIN

Logic inputs, except DIF_IN.

1.5

5

pF

1

COUT Output pin capacitance.

6

pF

1

CLK Stabilization

tSTAB

From VDD power-up and after input clock

stabilization or deassertion of PD# to 1st clock.

0.3

1.8

ms

1,2