MCP6231 datasheet(8/20 Pages) MICROCHIP

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MCP6231/2

DS21881B-page 8

 2004 Microchip Technology Inc.

FIGURE 3-4:

Recommended RISO Values

for Capactive Loads.

After selecting RISO for your circuit, double-check the

resulting

frequency

response

peaking

and

step

response overshoot. Evaluation on the bench and

simulations with the MCP6231/2 SPICE macro model

are very helpful. Modify RISO’s value until the response

is reasonable.

3.4

Supply Bypass

With this op amp, the power supply pin (VDD for

single-supply) should have a local bypass capacitor

(i.e., 0.01 µF to 0.1 µF) within 2 mm for good high-

frequency performance. It also needs a bulk capacitor

(i.e., 1 µF or larger) within 100 mm to provide large,

slow currents. This bulk capacitor can be shared with

other parts.

3.5

PCB Surface Leakage

In applications where low input bias current is critical,

Printed Circuit Board (PCB) surface leakage effects

need to be considered. Surface leakage is caused by

humidity, dust or other contamination on the board.

Under low humidity conditions, a typical resistance

between nearby traces is 1012

Ω. A 5V difference would

cause 5 pA, if current-to-flow. This is greater than the

MCP6231/2 family’s bias current at 25°C (1 pA, typ).

The easiest way to reduce surface leakage is to use a

guard ring around sensitive pins (or traces). The guard

ring is biased at the same voltage as the sensitive pin.

An example of this type of layout is shown in

Figure 3-5.

FIGURE 3-5:

Example Guard Ring Layout

for Inverting Gain.

Non-inverting Gain and Unity-Gain Buffer:

Connect the non-inverting pin (VIN+) to the

input with a wire that does not touch the

PCB surface.

Connect the guard ring to the inverting input

pin (VIN–). This biases the guard ring to the

common mode input voltage.

Inverting and transimpedance gain amplifiers

(convert current to voltage, such as photo

detectors):

Connect the guard ring to the non-inverting

input pin (VIN+). This biases the guard ring

to the same reference voltage as the op

amp (e.g., VDD/2 or ground).

Connect the inverting pin (VIN–) to the input

with a wire that does not touch the PCB

surface.

1.E+02

1.E+03

1.E+04

1.E+01

1.E+02

1.E+03

1.E+04

Normalized Load Capacitance; CL/GN (F)

10p

100p

10n

10k

100

GN = 1 V/V

GN = 2 V/V

GN ≥ 4 V/V

Guard Ring

VIN–VIN+

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