Figure 8. SPI output timing diagram

6.5.1

Watchdog

The IC is composed by two chips (Logic Stage and Process Stage) supplied by two independent and galvanic

isolated sources (VDD/GNDDD and VCC/GNDCC pins, respectively).

The IC provides a watchdog function in order to guarantee a safe condition for the Process Stage when VDD

(or GNDDD) supply voltage is missing. At the end of each SPI communication, the channel status register is

transferred to the Process Stage that both reset an internal timeout counter and turns ON/OFF the outputs

accordingly. If the Logic Stage does not update the output status within tWD, all the outputs of the Process Stage

are disabled until a new update request is received (this also happens if SS stays low for longer than tWD).

Independently of the SPI communication, the Logic Stage chip periodically sends a refresh signal to the Process

Stage chip. The refresh signal is also considered a valid update signal to reset the timeout counter on the Process

Stage, so the isolated side watchdog does not protect the system from a failure of the host controller (e.g., MCU

freezing).

Figure 9. Watchdog behavior

ISO808A, ISO808A-1

Slave select (SS)

DS14170 - Rev 1

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