Figure 7. OFF-time modulator - details

Referring to Figure 7, once the power switch ON-time is ended (Q signal goes low) the internal switch SW5 is

open and the constant current generator IR starts to charge linearly the capacitor CR. The resulting voltage VRAMP

is compared with the voltage VTH_RAMP, which is generated by the “Constant FSW“ circuitry based on the Q signal

duration (TON). As soon as the ramp voltage VRAMP reaches the VTH_RAMP voltage, the flip-flop is set and the

external power switch is turned on (Q signal goes high).

In other words, the power switch off-time (TOFF) is modulated based on the on-time information (TON) to keep

cycle-by-cycle constant the resulting switching frequency (FSW=1/TSW_TARGET):

TOFF = TSW_TARGET - TON.

Figure 8. Left OFF-time modulator timing – Line

cycle time scale

Figure 9. Right OFF-time modulator timing –

Switching cycle time scale

5.3

High voltage startup

The device embeds a High Voltage (HV) start-up circuitry, based on a high voltage N-channel FET as shown in

Figure 10, in order to supply the IC during the initial start-up phase before the self-supply winding is operating.

L4985

High voltage startup

DS13769 - Rev 3

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