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840S05AYILFT 数据表(PDF) 9 Page - Renesas Technology Corp |
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840S05AYILFT 数据表(HTML) 9 Page - Renesas Technology Corp |
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9 / 22 page ![]() 9 ©2016 Integrated Device Technology, Inc Revision A April 11, 2016 840S05I Data Sheet Parameter Measurement Information 3.3V Core/3.3V LVCMOS Output Load Test Circuit Output Skew RMS Period Jitter 3.3V Core/2.5V LVCMOS Output Load Test Circuit Bank Skew Output Slew Rate SCOPE Qx GND 1.65V±5% -1.65V±5% VDDA 1.65V±5% VDD, VDDO_A, VDDO_B, VDDO_REF ts k(o) V DDO_X 2 V DDO_Y 2 Qx Qy VOH VREF VOL Mean Period (First edge after trigger) Reference Point (Trigger Edge) 1 σ contains 68.26% of all measurements 2 σ contains 95.4% of all measurements 3 σ contains 99.73% of all measurements 4 σ contains 99.99366% of all measurements 6 σ contains (100-1.973x10-7)% of all measurements Histogram SCOPE Qx GND VDD 1.25V±5% -1.25V±5% 2.05V±5% VDDA 2.05V±5% VDDO_A, VDDO_B, VDDO_REF tsk(b) V DDO_X 2 V DDO_X 2 QX0 QX1 Where X is either Bank A or Bank B 20% 80% 80% 20% tR t F VF VR tSLEW = VR/tR QA[1:0], QB[1:0] |
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