STUW81300 datasheet(53/63 Pages) STMICROELECTRONICS

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DS11314 Rev 7

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STuW81300

Application information

8.2

Thermal PCB design considerations

The STuW81300 QFN package offers a low thermal resistance (

θJC ~3 °C/W on a JEDEC

Multi-Layer Board). Preferred thermal flow in QFN package is through the bottom central

pad.

The central thermal pad provides a solderable surface on the top of the PCB (for soldering

the package die paddle on the board). Thermal vias are needed to provide a thermal path to

the inner and bottom layers of the PCB in order to remove/dissipate the heat. The size of the

thermal pad can be matched with the exposed die paddle, or it may be smaller taking into

consideration clearance for vias to route the inner row signals.

A PCB can be designed to achieve a thermal impedance of 2 to 4 °C/W through a 1.6 mm

(.063”) thick FR-4 type PCB (a reliable, low cost solution).

For example the ST EVAL KIT uses a 0.8 mm thick PCB with a thermal impedance of

~50 °C/W for a single via filled with solder. 25 vias are used, giving a thermal impedance of

~2 °C/W with solder-filled vias (50 °C/W divided by 25 vias).

Using a plate on the underside of the PCB (a common solution in STuW81300 applications,

as the plate is typically the metal housing of the application assembly) brings the total

thermal resistance (junction to housing in the customer application) below 10 °C/W.

As the typical power dissipation of the STuW81300 is approximately 1.5 W, at maximum

specified ambient temperature (85 °C) a junction temperature of ~100 °C is attainable. This

is well below the maximum specified value (125 °C) to ensure safe operation of the

STuW81300 in worst-temperature conditions.

The ST EVAL KIT is not provided with additional heatsinking, and the thermal resistance

(

θJA) measured in the EVAL BOARD is ~30 °C/W.

8.3

Robust VCO calibration over full temperature range

Some applications require a fixed frequency whilethe lock condition, without any

phase/frequency jumps, even if temperature drift occurs over the whole operating

temperature range.

In such cases, the capability of the STuW81300 the specific VCO and sub-bands selected

by the VCO auto-calibration procedure - defined by the

ΔTLOCK parameter (see Table 6:

Electrical specifications).

I, a factory calibration at fixed/controlled temperature may be applied.

The concept is to run the standard VCO auto-calibration procedure (after writing the ST0

the field, the STuW81300 is set up using a manual VCO calibration, recalling the VCO and

sub-band data previously stored in the application memory.

In this way, with a good thermal PCB design to limit the maximum junction temperature to

100 °C (see Section 8.2: Thermal PCB design considerations), the STuW81300 VCO is

calibrated virtually at 25 °C, regardless of the effective temperature during in-field setup.

STUW81300 数据表(PDF) 53 Page - STMicroelectronics

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