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ST70134A 数据表(PDF) 5 Page - STMicroelectronics |
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ST70134A 数据表(HTML) 5 Page - STMicroelectronics |
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5 / 22 page  ST70134A 5/22 Table 2 : Pin Functions Numbers Name Function PCB connection Supply ANALOG INTERFACE 24 VRAP Positive Voltage Reference ADC Decoupling network AVDD3 25 VREF Ground Reference ADC Decoupling network AVDD3 26 VRAN Negative Voltage Reference ADC Decoupling network AVDD3 31 TXP Pre Driver Output Line driver input AVDD4 32 TXN Pre Driver Output Line driver input AVDD4 38 AGND Virtual Analog Ground (AVDD/2 = 1.65V) Decoupling network AVDD5 44 VCOC VCODAC Time Constant Capacitor VCODAC cap. AVDD5 45 GC0 External Gain Control Output LSB - AVDD5 46 GC1 External Gain Control Output MSB - AVDD5 47 RXN0 Analog Receive Negative Input Gain 0 Echo filter output AVDD5 48 RXP0 Analog Receive Positive Input Gain 0 Echo filter output AVDD5 49 RXN1 Analog Receive Negative Input Gain 1 (Most Sensitive Input) Echo filter output AVDD5 50 RXP1 Analog Receive Positive Input Gain 1 (Most Sensitive Input) Echo filter output AVDD5 53 IREF Current Reference TX DAC/DACE Decoupling network AVDD2 55 IVCO Current Reference VCO DAC VCO bias network AVDD1 56 VCXO VXCO Control Current VCXO filter AVDD1 59 XTALI XTAL Oscillator Input Pin Crystal + varicap AVDD1 60 XTALO XTAL Oscillator Output Pin Crystal + varicap AVDD1 DIGITAL INTERFACE 1 TX1 Digital Transmit Input, Parallel Data - DVDD2 2 TX0 Digital Transmit Input, Parallel Data - DVDD2 7 CTRLIN Serial Data Input (Settings) Async Interface DVDD2 9 CLKM Master Clock Output, f = 35.328MHz Load = CL<30pF DVDD2 10 CLNIB Nibble Clock Output, f = 17.664MHz (OSR = 2) or ground (OSR = 4) Load = CL<30pF DVDD2 11 CLWD Word Clock Output, f = 8.832/4.416MHz Load = CL<30pF DVDD2 12 RX3 Digital Receive Output, Parallel Data Load = CL<30pF DVDD2 13 RX2 Digital Receive Output, Parallel Data Load = CL<30pF DVDD2 14 RX1 Digital Receive Output, Parallel Data Load = CL<30pF DVDD2 15 RX0 Digital Receive Output, Parallel Data Load = CL<30pF DVDD2 18 PDOWN Power Down Select, "1" = Power Down Power Down Input DVDD2 20 RESETN Reset Pin (Active Low) RC- Reset DVDD2 22 GP0 General Purpose Output 0 (on AVDD 1) Echo filter output AVDD 33 GP1 General Purpose Output 1 (on AVDD 1) Echo filter output AVDD 43 GP2 General Purpose Output 2 (on AVDD 1) Echo filter output AVDD 63 TX3 Digital Transmit Input, Parallel Data Load = CL<30pF DVDD2 64 TX2 Digital Transmit Input, Parallel Data Load = CL<30pF DVDD2 19, 21 RES RESERVED Must Be Connected to DVSS (Input) - 36, 37, 39, 40, 57 RES RESERVED Must Be Connected to AVSS (Input) - |
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