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ICS83115BRLF 数据表(PDF) 1 Page - Renesas Technology Corp |
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ICS83115BRLF 数据表(HTML) 1 Page - Renesas Technology Corp |
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1 / 12 page ![]() DATA SHEET Low Skew, 1-TO-16 LVCMOS/LVTTL Fanout Buffer 83115 83115 Rev C 3/20/15 1 ©2015 Integrated Device Technology, Inc. 4 4 Q15 Q14 Q13 Q12 Q11 Q10 Q9 Q8 IN Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 OE0 GND OE1 OE2 VDD General Description The 83115 is a low skew, 1-to-16 LVCMOS/ LVTTL Fanout Buffer from IDT. The 83115 single-ended clock input accepts LVCMOS or LVTTL input levels. The 83115 operates at full 3.3V supply mode over the commercial temperature range. Guaranteed output and part-to-part skew characteristics make the 83115 ideal for those clock distribution applications demanding well defined performance and repeatability. Features • Sixteen LVCMOS / LVTTL outputs, 15 output impedance • One LVCMOS / LVTTL clock input • Maximum output frequency: 200MHz • All inputs are 5V tolerant • Output skew: 250ps (maximum) • Part-to-part skew: 800ps (maximum) • Additive phase jitter, RMS: 0.09ps (typical) • Full 3.3V operating supply • 0°C to 70°C ambient operating temperature • Available in lead-free (RoHS 6) package 83115 28-Lead SSOP, 150mil 9.9mm x 3.9mm x 1.5mm package body R Package Top View 1 2 3 4 5 6 7 28 27 26 25 24 23 22 8 9 10 11 12 13 14 21 20 19 18 17 16 15 Q15 Q14 Q13 Q12 Q11 Q10 Q9 Q8 GND GND OE2 OE0 VDD VDD VDD VDD Q1 Q2 Q3 Q4 Q5 Q6 Q7 IN GND GND Q0 OE1 Pin Assignment Block Diagram |
类似零件编号 - ICS83115BRLF |
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类似说明 - ICS83115BRLF |
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