DA16200 datasheet(39/154 Pages) RENESAS

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DA16200

Ultra Low Power Wi-Fi SoC

Datasheet

Revision 3.6

04-Jan-2023

CFR0011-120-00

39 of 153

QFN and fcCSP Package

Input Selection = 0

Input Selection = 1

GPIOA7

GPIOA8

GPIOA9

GPIOC6

GPIOA10

GPIOC7

GPIOA11

GPIOC8

For more information on the wake-up source selection, see the input selection register:

0x50091008[25:16].

The wake-up controller is in the RTC block. RTC registers can set several parameters and identify

which pin is used to wake up the SoC by checking the status register after wake-up.

DA16200 has another wake-up function using analog sources, which is described in Section 9.8.4.

Using the Aux-ADC, DA16200 detects whether it exceeds the predefined threshold value. If it detects

the wanted condition, it will wake up from a Sleep mode. Four ports (GPIOA[3:0]) are used for this

function.

7.4.2

Retention I/O Function

DA16200 I/O supports a retention mode where the I/O cells retain their previous values at the core

side inputs when in Sleep mode 2 or Sleep mode 3.

Retention mode for the I/O cells is controlled by three bits in the retention enable register of the RTC

block (0x5009_1018:BIT[27:24]).

To maintain a specific GPIO value when in Sleep mode 2 or Sleep mode 3, the specific bit controlling

the I/O power for it must be enabled in the retention enable register.

For example, to maintain a HIGH value on GPIOA4 during Sleep mode 2 or Sleep mode 3, set the

value of GPIOA4 to HIGH and also set the retention enable register BIT[25] to HIGH.

A description of the retention enable register and the I/O power domains it controls can be found in

Table 30.

Table 30: I/O Power Domain

[25] DIO1

[26] DIO2

[27] FDIO

GPIOA[11:4]

GPIOC[8:6]

F_CLK

TCLK/TMS

F_CSN

UART0_RXD/UART0_TXD

F_IO0 to F_IO3

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