Philips Semiconductors

Product specification

87C524/87C528

80C51 8-bit microcontrollers

1999 Jul 23

13

SYMBOL

PARAMETER

INPUT

OUTPUT

SCL TIMING CHARACTERISTICS

START condition hold time

Note 2

≥ 4.0µs

SCL LOW time

Note 2

≥ 4.7µs

SCL HIGH time

≥ 4.0µs

SCL rise time

Note 5

≤ 1.0µs

SCL fall time

≤ 0.3µs

SDA TIMING CHARACTERISTICS

Data set-up time

≥ 250ns

Note 2

≥ 250ns

Data hold time

≥ 0ns

Note 2

≥ 0ns

Repeated START set-up time

Note 2

≥ 4.7µs

STOP condition set-up time

Note 2

≥ 4.0µs

Bus free time

Note 2

≥ 4.7µs

SDA rise time

Note 5

≤ 1.0µs

SDA fall time

≤ 0.3µs

NOTES:

SCL pulse may be timed by software.

4. Spikes on SDA and SCL lines with a duration of less than 4

5. The rise time is determined by the external bus line capacitance and pull-up resistor, it must be

≤ 1µs.

6. The maximum capacitance on bus lines SDA and SCL is 400pF.