Table 7. Receiver electrical characteristics

Symbol

Parameter

Test conditions

Min. Typ. Max. Unit

VTH

Receiver differential

threshold voltage

VCM=-7 V to 12 V, DE = 0

-0.2

-0.015

V

ΔVTH

Receiver input hysteresis

VCM=0 V

30

µV

VOH

Receiver output high voltage

IOUT = -4 mA, VID = 200 mV, (Figure 8. Drive enable and

disable times waveforms)

2

V

VOL

Receiver output low voltage

IOUT= 4 mA, VID = -200 mV, (Figure 3. Driver VOD with

varying common mode voltage test load)

0.4

V

IOZR

3-state (high impedance)

output current at receiver

VCC= 3.6 V, VO = 0 V to VCC

±1

µA

RRIN

Receiver input resistance

VCM = -7 V to 12 V

24

kΩ

IOSR

Receiver short-circuit current

VRO = 0 V to VCC

7

60

mA

Table 8. Driver switching characteristics

Symbol

Parameter

Test conditions

Min. Typ. Max. Unit

DR

Maximum data rate

12

15

Mbps

tDD

Differential output delay

RL= 60 Ω, CL= 15 pF, (Figure 4. Receiver VOH and VOL test

circuit and Figure 5. Drive differential output delay transition

time test circuit)

18

30

ns

tTD

Differential output

transition time

RL= 60 Ω, CL= 15 pF, (Figure 4. Receiver VOH and VOL test

circuit and Figure 5. Drive differential output delay transition

time test circuit)

12

20

ns

tPLH

tPHL

Propagation delay

RL= 27 Ω, CL= 15 pF, (Figure 8. Drive enable and disable

times waveforms and Figure 9. Drive propagation time test

circuit)

18

30

ns

tPDS

|tPLH - tPHL|propagation

delay skew(1)

RL= 27 Ω, CL= 15 pF, (Figure 8. Drive enable and disable

times waveforms and Figure 9. Drive propagation time test

circuit)

2

5

ns

tPZL

Output enable time

RL= 110 Ω, (Figure 10. Drive propagation time waveform and

Figure 11. Drive enable and disable times test circuit (RL=

110 Ω))

19

35

ns

tPZH

Output enable time

RL= 110 Ω, (Figure 10. Drive propagation time waveform and

Figure 11. Drive enable and disable times test circuit (RL=

110 Ω))

30

50

ns

tPHZ

Output disable time

RL= 110 , (Figure 6. Drive differential output delay transition

time waveform and Figure 7. Drive enable and disable times

test circuit)

19

35

ns

tPLZ

Output disable time

RL= 110 Ω (Figure 10. Drive propagation time waveform and

Figure 11. Drive enable and disable times test circuit (RL=

110 Ω))

30

50

ns

tSKEW

Differential output delay

skew

1

3

ns

tZH(SHDN)

Driver enable from

shutdown to output high

30

50

ns

tZL(SHDN)

Driver enable from

shutdown to output low

19

35

ns

1. Measured on |tPLH(A)-tPHL(A)| and |tPLH(B)-tPHL(B)|

ST1480US

Electrical characteristics

DS13697 - Rev 1

page 6/21