6.42

IDT709279/69S/L

Preliminary

High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

13

Timing Waveform of Pipelined Read with Address Counter Advance(1)

Timing Waveform of Flow-Through Read with Address Counter Advance(1)

NOTES:

1. CE0, OE, UB, and LB = VIL; CE1, R/W, and CNTRST = VIH.

2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then the data

output remains constant for subsequent clocks.

ADDRESS

An

CLK

DATAOUT

Qx - 1

(2)

Qx

Qn

Qn + 2

(2)

Qn + 3

ADS

CNTEN

tCYC2

tCH2

tCL2

3243 drw 15

tSA

tHA

tSAD tHAD

tCD2

tDC

READ

EXTERNAL

ADDRESS

READ WITH COUNTER

COUNTER

HOLD

tSAD tHAD

tSCN tHCN

READ

WITH

COUNTER

Qn + 1

ADDRESS

An

CLK

DATAOUT

Qx

(2)

Qn

Qn + 1

Qn + 2

Qn + 3

(2)

Qn + 4

ADS

CNTEN

tCYC1

tCH1

tCL1

3243 drw 16

tSA

tHA

tSAD tHAD

READ

EXTERNAL

ADDRESS

READ WITH COUNTER

COUNTER

HOLD

tCD1

tDC

tSAD tHAD

tSCN tHCN

READ

WITH

COUNTER