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DSP56321T/D 数据表(PDF) 49 Page - NXP Semiconductors |
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DSP56321T/D 数据表(HTML) 49 Page - NXP Semiconductors |
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49 / 88 page  2-25 AC Electrical Characteristics 450 TXC rising edge to FST out (word-length) high 0.25 × T ECCX 0.25 × T ECCI — — 6.8 9.1 — — 6.3 8.3 x ck i ck ns 451 TXC rising edge to FST out (word-length) low 0.25 × T ECCX 0.25 × T ECCI — — 6.8 9.1 — — 6.3 8.3 x ck i ck ns 452 TXC rising edge to data out enable from high impedance 0.25 × T ECCX 0.25 × T ECCI — — 6.8 9.1 — — 6.3 8.3 x ck i ck ns 453 TXC rising edge to Transmitter #0 drive enable assertion 0.25 × T ECCX 0.25 × T ECCI — — 6.8 9.1 — — 6.3 8.3 x ck i ck ns 454 TXC rising edge to data out valid 0.25 × T ECCX 0.25 × T ECCI — — 6.8 9.1 — — 6.3 8.3 x ck i ck ns 455 TXC rising edge to data out high impedance3 0.25 × T ECCX 0.25 × T ECCI — — 6.8 9.1 — — 6.3 8.3 x ck i ck ns 456 TXC rising edge to Transmitter #0 drive enable deassertion3 0.25 × T ECCX 0.25 × T ECCI — — 6.8 9.1 — — 6.3 8.3 x ck i ck ns 457 FST input (bl, wr) setup time before TXC falling edge2 0.2 × T ECCX 0.2 × T ECCI 5.5 7.3 — — 5 6.7 — — x ck i ck ns 458 FST input (wl) to data out enable from high impedance TBD — TBD — TBD — ns 459 FST input (wl) to Transmitter #0 drive enable assertion TBD — TBD — TBD — ns 460 FST input (wl) setup time before TXC falling edge 0.2 × T ECCX 0.2 × T ECCI 5.5 7.3 — — 5 6.7 — — x ck i ck ns 461 FST input hold time after TXC falling edge 0.15 × T ECCX 0.15 × T ECCI 4.1 5.5 — — 3.8 5.0 — — x ck i ck ns 462 Flag output valid after TXC rising edge 0.25 × T ECCX 0.25 × T ECCI — — 6.8 9.1 — — 6.3 8.3 x ck i ck ns Notes: 1. For the internal clock, the external clock cycle is defined by the instruction cycle time (timing 7 in Table 2-5 on page 2-5) and the ESSI control register. TECCX must be ≥ TC × 3, in accordance with the note below Table 7-1 in the DSP56321 Reference Manual. TECCI must be ≥ TC × 4, in accordance with the explanation of CRA[PSR] and the ESSI Clock Generator Functional Block Diagram shown in Figure 7-3 of the DSP56321 Reference Manual. 2. The word-length-relative frame sync signal waveform operates the same way as the bit-length frame sync signal waveform, but spreads from one serial clock before the first bit clock (same as the Bit Length Frame Sync signal) until the one before last bit clock of the first word in the frame. 3. Periodically sampled and not 100 percent tested 4. VCCQH = 3.3 V ± 0.3 V, VCCQL = 1.6 V ± 0.1 V; TJ = 0°C to +85°C, CL = 50 pF 5. TXC (SCK Pin) = Transmit Clock RXC (SC0 or SCK Pin) = Receive Clock FST (SC2 Pin) = Transmit Frame Sync FSR (SC1 or SC2 Pin) Receive Frame Sync 6. i ck = Internal Clock; x ck = External Clock i ck a = Internal Clock, Asynchronous Mode (asynchronous implies that TXC and RXC are two different clocks) i ck s = Internal Clock, Synchronous Mode (synchronous implies that TXC and RXC are the same clock) 7. In the timing diagrams below, the clocks and frame sync signals are drawn using the clock falling edge as a the first reference. Clock and frame sync polarities are programmable in Control Register B (CRB). Refer to the DSP56321 Reference Manual for details. Table 2-12. ESSI Timings (Continued) No. Characteristics4, 6 Symbol Expression 220 MHz 240 MHz Cond- ition5 Unit Min Max Min Max Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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