DA9213 datasheet(36/63 Pages) RENESAS

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DA9213, DA9214, and DA9215

Multi-Phase 5A/Phase DC-DC Buck Converter

Datasheet

Revision 3.4

10-Feb-2022

CFR0011-120-00

36 of 62

The communication on the 2-WIRE bus always takes place between two devices, one acting as the

master and the other as the slave. The DA9213, DA9214, and DA9215 will only operate as a SLAVE.

In contrast to the 4-WIRE mode, the 2-WIRE interface has direct access to two pages of the register

map (up to 256 addresses). The register at address zero on each page is used as a page control

to page 0 was selected by asserting control REVERT. Unless REVERT was asserted after modifying

the active page, it is recommended to read back the page control register to ensure that future data

exchange is accessing the intended registers.

In 2-WIRE operation DA9213, DA9214, and DA9215 offer an alternative way to access register page

2 and page 3. It removes the need for preceding page selection writes by incrementing the device

write/read address by one (default 0xD2/0xD3) for any direct access of page 2 and page 3 (page 0

and 1 access requires the basic write/read device address with the MSB of REG_PAGE to be 0).

7.4.3

Details of the 2-WIRE Control Bus Protocol

All data is transmitted across the 2-WIRE bus in groups of eight bits. To send a bit the SDA line is

driven towards the intended state while the SCL is LOW (a low on SDA indicates a zero bit). Once

the SDA has settled, the SCL line is brought HIGH and then LOW. This pulse on SCL clocks the

SDA bit into the receiver’s shift register.

A two-byte serial protocol is used containing one byte for address and one byte data. Data and

address transfer are transmitted MSB first for both read and write operations. All transmissions begin

with the START condition from the master while the bus is in IDLE state (the bus is free). It is initiated

by a high to low transition on the SDA line while the SCL is in the high state (a STOP condition is

indicated by a low to high transition on the SDA line while the SCL is in the high state).

SCL

SDA

Figure 25: Timing of 2-WIRE START and STOP Condition

The 2-WIRE bus is monitored by DA9213, DA9214, and DA9215 for a valid SLAVE address

whenever the interface is enabled. It responds immediately when it receives its own slave address.

The acknowledge is done by pulling the SDA line low during the following clock cycle (white blocks

marked with A in Figure 26 to Figure 30).

The protocol for a register write from master to slave consists of a start condition, a slave address

with read/write bit and the 8-bit register address followed by eight bits of data terminated by a STOP

condition. DA9213, DA9214, and DA9215 respond to all bytes with Acknowledge. This is illustrated in

Figure 26.

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