EL4331

FN7162 Rev 1.00

Page 7 of 10

May 12, 2004

Applications Information

Circuit Operation

Each multiplexing amplifier has two input stages. The

multiplexing amplifiers switch from their “A” inputs to their “B”

inputs under control of the common A/B select pin. The

switching has a make before break action. Each amplifier is

internally connected for unity gain, allowing larger switching

matrixes to be built up. Note however, that each amplifier likes

to see a load of 250

 or less; load resistances higher than this,

can lead to excessive peaking. Load capacitance should be

kept down below 40pF, and 40pF requires a load resistance of

150

 to keep the output from excessive peaking. Higher

capacitive loads can best be driven using a series resistor to

isolate the amplifier from the reactive load.

The ground pins are used as a reference for the logic controls.

Both A/B and PD are referenced to ground. The supplies do

not have to be symmetrical around ground, but the logic inputs

are referred to the ground pins, and the logic swing must not

exceed the +V supply. Due to the fact that all three channels

share common control pins, the three grounds have to be at

the same potential. One third of the 1mA that PD will sink (at

5V) will be seen at each ground pin. Also, the individual

grounds are internally connected to their channel

compensation capacitor in an effort to keep crosstalk low.

A/B Switching

Referring to the photographs showing the 0V–0V switching

glitches, it will be noted that slower edges on the A/B control

pin result in switching glitches of somewhat less total energy.

The switching action is a make-before-break, so the two inputs

essentially get mixed at the output for a few nanoseconds.

Note that the two inputs are buffered, so there is no component

of one input injected into the other input. The input impedance

does not depend on whether an input has been selected.

Power-Down

Referring to the photographs of the power-down function and

Figure 4, it will be noted that there is a considerable glitch in

the output as the part powers down. It will also be noted that

the power-down time is considerably longer than power up,

1µs compared to 150ns. In power-down mode, the whole

amplifier, its reference and bias lines are all powered down. At

the same time, the output stage has been configured so that

the powered down output appears as a high impedance. This

allows circuits such as the multiplexer shown in application #4

to be realized, although the price is the significant output

disturbance as one part turns on before the other has fully

turned off.

Single Supply Operation

Due to the fact that video signals often have negative sync

levels and invariably require ground to be within the signal

swing, running the EL4331 on a single supply rail

compromises many aspects of its performance. It is difficult to

generate a solid, clean, pseudo ground a few volts away from

ground without using more power, and components than

simply providing a negative power rail. A signal ground has to

be capable of handling all the return currents from all the

inputs, as well as the outputs, from DC to frequencies in

excess of 400MHz. While this is by no means impossible, a

negative rail can be generated from a standard +5V rail for a

couple of dollars and a square inch, or less, of board space.

However, a pseudo ground can be derived with for example an

LM336, to give an “AC ground” 2.5V above 0V. The logic

inputs will need some form of level shifting to ensure that the

logic “1” and “0” specifications can be met. The pseudo ground

must be well bypassed to the real ground; note that the pseudo

ground will have to sink/source all the current that flows in the

internal compensation capacitors during slewing. This can

easily be several milliamps in a few nanoseconds. If the

pseudo ground “moves” because one channel is forcing

current into the derived ground, cross-talk into the other two

channels will become very significant.

Application Circuit #1

Figure 1 shows a very high speed RGB (or YUV) multiplexer.

Two video sources can be displayed on one monitor with the

only stipulation that the video sources have to be synchronous.

An example is a picture-in-picture, or “window” is generated

Pin Descriptions

PIN NAME

PIN DESCRIPTION

A1, A2, A3

“A” inputs to amplifiers 1, 2 and 3 respectively

B1, B2, B3

“B” inputs to amplifiers 1, 2 and 3 respectively

GND1, GND2, GND3

These are the individual ground pins for each channel.

OUT1, OUT2, OUT3

Amplifier outputs. Note there is no short circuit protection.

VCC

Positive power supply. Typically +5V.

VEE

Negative power supply, typically -5V.

A/B

Common input select pin, a logic high selects the “A” inputs, logic low selects the “B” inputs. If left to float, this pin

will float high and the “A” channels will be selected.

PD

A logic low puts the part into its power-down mode. Note that when this pin is at a logic high (+5V), it will sink typically

1mA. When pulled low, it will source a few µA, typically < 25µA. This pin should not be left floating.