2

ICS94258

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Pin Descriptions

Notes:

1:

Internal Pull-up Resistor of 120K to 3.3V on indicated inputs

2:

Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor

to program logic Hi to VDD or GND for logic low.

3:

Internal Pull-down resistor of 120K to GND on indicated inputs.

PIN NUMBER

PIN N AME

TYPE

DESCRIPTION

1, 45

V DDL

PWR

Pow er supply pins, nominal 2.5V

2

IOAPIC

OUT

2.5V clock outputs

4

X1

IN

Crystal input,nominally 14.318M Hz.

5

X2

OUT

Crystal output, nominally 14.318M H z.

3, 11, 16, 23, 29,

34, 41, 48

GN D

PWR

G round pins

6, 8, 17, 21, 28,

35, 40

VD D

PWR

Pow er supply pins, nominal 3.3V

FS0

2, 3

IN

Frequency select pin, 1X or 2X strength (default = 2X).

REF

OUT

14.318 M H z reference clock.

FS1

2, 3

IN

Frequency select pin.

AG P0

OUT

A GP outputs defined as 2X PCI frequency. These may not be stopped.

10

AG P1

OUT

A GP outputs defined as 2X PCI frequency. These may not be stopped.

PCICLK_F

OUT

Free running PCICLK not stoped by PCI_STOP#

FS2

1, 3

IN

Frequency select pin.

PCICLK2

OUT

PCI clock output

RESET#

OUT

Real time system reset signal for frequency value or watchdog timmer

timeout. This signal is active low. Output is selectable via I

2

C Byte 5 bit7

14, 13

PCICLK

(1, 0)

OUT

PCI clock outputs.

PCICLK3

OUT

PCI clock output.

MODE

1, 3

IN

Function select pin, 1=Desktop M ode, 0=M obile M ode.

EPCICLK_F

OUT

Free running early PCI clock output (default)

PCICLK4

OUT

PCI clock output.

PD #

1

IN

A synchronous active low input pin used to power down the device into a low

power state. The internal clocks are disabled and the VCO and the crystal are

stopped. The latency of the power down w ill not be greater than 3ms.

(See M ODE table for further information.)

PCICLK5

OUT

PCI clock output. This pin is active when M ODE = 0 (default)

FS3

2, 3

IN

Frequency select pin.

48M Hz

OUT

48M Hz output clock.

24

SCLK

IN

Clock input of I

2

C input, 5V tolerant input

PD #

1

IN

A synchronous active low input pin used to power down the device into a low

power state. The internal clocks are disabled and the VCO and the crystal are

stopped. The latency of the power down w ill not be greater than 3ms.

(See M ODE table for further information.)

SD RA M 12

OUT

SDRAM clock output. This pin is active when M ODE = 1.

CPU_STOP#

1

IN

This asynchronous input halts CPU clock at logic "0" level when driven low,

the stop selection can be programmed through I

2

C. This is activated when

M ODE = 0 (default)

SD RA M 11

OUT

SDRAM clock output. This pin is active when M ODE = 1.

PCI_STOP#

1

IN

Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level,

when input low. This is activated when M OD E = 0 (default)

SD RA M 10

OUT

SDRAM clock output. This pin is active when M ODE = 1.

SELPCI_F

IN

Selects EPCICLK _F This pin is active when M O DE = 0 (default).

SDRAM 9

OUT

SDRAM clock output. This pin is active when M ODE = 1.

31, 32, 33, 36, 37,

38, 39, 42, 43

SDRAM ( 8:0 )

OUT

SDRAM clock outputs.

44

SDA TA

I/O

Data pin for I

2

C circuitry 5V tolerant

46

CPUCLK _F

OUT

Free running CPU clock. N ot affected by CPU_STO P#.

47

CPUCLK

OUT

2.5V CPU clock.

30

19

9

7

27

26

12

25

22

18

20

15