ICS844256DGI REVISION A AUGUST 5, 2010

13

©2010 Integrated Device Technology, Inc.

ICS844256DI Data Sheet

FEMTOCLOCK® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER

Schematic Example

Figure 6 shows an example of ICS844256DI application schematic.

In this example, the device is operated at VDD = VDDO = 3.3V. The

18pF parallel resonant 25MHz crystal is used. The C1 and C2 = 27pF

are recommended for frequency accuracy. For different board

layouts, the C1 and C2 may be slightly adjusted for optimizing

frequency accuracy. Two examples of LVDS for receiver without

built-in termination are shown in this schematic.

Figure 6. ICS844256DI Schematic Layout

VDD

VDDO

RD2

1K

+

-

VDD

R4

50

RD1

Not Install

C7

0.01uF

VDD

N_SEL0

Q2

1 8 p F

C8

0.1uF

Q0

Zo = 50 Ohm

Alternate

LVDS

Termination

R2

10

nQ4

R1

100

VDDA

FB_SEL

C5

0.01uF

Zo = 50 Ohm

PLL_BYPASS

Zo = 50 Ohm

To Logic

Input

pins

nQ5

C4

0.01u

RU1

1K

nQ2

VDD= VDDO=3.3V

Set Logic

Input to

'1'

Set Logic

Input to

'0'

VDDO

nQ1

C1

27pF

N_SEL1

RU2

Not Install

Q3

X1

25MHz

nQ3

C2

27pF

VDD

VDD

Q1

C3

10uF

C6

0.01uF

U1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

VDDO

VDDO

nQ2

Q2

nQ1

Q1

nQ0

Q0

PLL_BYPASS

VDDA

VDD

FB_SEL

XTAL_IN

XTAL_OUT

N_SEL0

GND

GND

N_SEL1

nQ5

Q5

nQ4

Q4

nQ3

Q3

+

-

Zo = 50 Ohm

Q4

To Logic

Input

pins

Q5

nQ0

R3

50

Logic Control Input Examples