6.5 Electrical Characteristics (continued)

VCC = 2.5, 3.3 and 5 V, VEE = 0 V, VCM = VEE + 300 mV, CL = 5 pF probe capacitance, typical at TA = 25°C (unless otherwise

noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Latching/Adjustable Hysteresis

VHYST

Input hysteresis voltage

VHYST = Logic High

0

mV

VHYST

Input hysteresis voltage

RHYST = Floating

3

mV

VHYST

Input hysteresis voltage

RHYST = 150 kΩ

30

mV

VHYST

Input hysteresis voltage

RHYST = 56 kΩ

60

mV

VIH_LE

LE pin input high level

TA = –40℃ to +125℃

VEE + 1.5

V

VIH_LE (TLV3603E)

LE pin input high level

TA = –55℃ to +125℃

VEE + 1.5

V

VIL_LE

LE pin input low level

TA = –40℃ to +125℃

VEE + 0.35

V

VIL_LE (TLV3603E)

LE pin input low level

TA = –55℃ to +125℃

VEE + 0.35

V

IIH_LE

LE pin input leakage current

VLE = VCC

TA = –40℃ to +125℃

15

uA

IIH_LE (TLV3603E)

LE pin input leakage current

VLE = VCC

TA = –55℃ to +125℃

15

uA

IIL_LE

LE pin input leakage current

VLE = VEE,

TA = –40℃ to +125℃

40

uA

IIL_LE (TLV3603E)

LE pin input leakage current

VLE = VEE,

TA = –55℃ to +125℃

40

uA

tSETUP

Latch setup time

–1.4

ns

tHOLD

Latch hold time

7.2

ns

tPL

Latch to OUT delay

7

ns

(1)

Ensured by characterization

(2)

Differential propagation delay is defined as the larger of the two:

ΔtPDLH = tPDLH(MAX) – tPDLH(MIN)

ΔtPDHL = tPDHL(MAX) – tPDHL(MIN)

where (MAX) and (MIN) denote the maximum and minimum values

of a given measurement across the different comparator channels.

6.6 Timing Diagrams

IN+

IN-

V

OUT

V

OVERDRIVE

V

UNDERDRIVE

V

UNDERDRIVE

V

OVERDRIVE

50%

t

R

t

F

t

PLH

t

PHL

90%

10%

Figure 6-1. General Timing Diagram

www.ti.com

TLV3601, TLV3602, TLV3603, TLV3603E

SNOSDB1E – JUNE 2021 – REVISED APRIL 2023

Copyright © 2023 Texas Instruments Incorporated

Submit Document Feedback

9

Product Folder Links: TLV3601 TLV3602 TLV3603 TLV3603E