| 数据搜索系统,热门电子元器件搜索 |
|
L9961 数据表(PDF) 39 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
L9961 数据表(HTML) 39 Page - STMicroelectronics |
|
39 / 65 page ![]() 3.8.3 MCU emergency reset (FAULTN_SAFE) MCU should normally manage the communication with battery charger, ensuring cells are properly charged to 100% state of charge. In case MCU operation fails, the battery cells could be overcharged, leading to fire/ explosion hazard. L9961 can reset the MCU should a cell overvoltage condition be detected. This is done connecting the FAULTN_SAFE open-drain output to the MCU reset pin (active low). When overvoltage failures are directed to FAULTN_SAFE pin, the output is pulled low for TFAULTN_SAFE_LOW to allow proper reset of the MCU. 3.8.3.1 Electrical parameters All parameters are tested and guaranteed in the following conditions, unless otherwise noted: VB according to the operating range of Table 2; TJ according to the operating range of Table 5. Table 29. Digital output electrical characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit Pin TFAULTN_SAFE_LOW FAULTN_SAFE low interval Tested by SCAN 85 104 120 μs FAULTN_SAFE 3.8.4 Electrical parameters All parameters are tested and guaranteed in the following conditions, unless otherwise noted: VB according to the operating range of Table 2; TJ according to the operating range of Table 5. Table 30. Digital output electrical characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit Pin VIN_L Low input level Valid for FAULTN, SDA, SCL Slow rising ramp on input pin 0.8 - 1.8 V SCL, FAULTN VIN_HYS Input hysteresis Valid for FAULTN, SDA, SCL Input considered high when VIN > VIN_L + VIN_HYS 0.1 - 0.5 V SCL, FAULTN VOUT_L Low output level IOUT = 2 mA 0 - 0.4 V RDY VOUT_H High output level IOUT = 2 mA VREG-0.4 - VREG V RDY TOUT_RISE Output rise time Valid for RDY Cload=120 pF From 20 to 80% of final value 5 - 35 ns RDY TOUT_FALL Output fall time Valid for RDY. Cload=120 pF From 80 to 20% of initial value 5 - 35 ns RDY VOPEN_DRAIN Open-drain equivalent ON resistance measurement Valid for SDA, FAULTN, FAULTN_SAFE, OD IOD=2 mA 0.02 - 0.15 V SDA, FAULTN, OD, FAULTN_SAFE 3.9 I2C communication interface L9961 uses an I2C slave peripheral interface to communicate with a host MCU on an addressed I2C bus. The I2C peripheral uses two lines to implement communication: • SCL (Serial CLock): a digital input receiving clock from the master unit of the I2C bus. • SDA (Serial DAta): a digital input/output used for sending and receiving data clocked by the master unit of the I2C bus L9961 I2C communication interface DS14012 - Rev 3 page 39/65 |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |