ZLED7015 Datasheet

© 2016 Integrated Device Technology, Inc.

19

April 20, 2016

PGND

VP

AGND

AGND

EN

LX

VDD

NC

FB

OVP

5

ESD/Latch-Up-Protection

All high voltage pins (1, 4, 5, 9, and 10) have an ESD protection of >± 2500V according to the Human Body Model

(HBM). The ESD test follows the Human Body Model based on MIL 883-H, Method 3015.8

All low voltage pins (2, 3, 6, 7, and 8) have an ESD protection of >± 4000V according to the Human Body Model

(HBM). The ESD test follows the Human Body Model based on MIL 883-H, Method 3015.8

All pins pass the latch-up test based on the JEDEC Standard No. 78B, December 2008.

6

Pin Configuration and Package

The ZLED7015 package is an MSOP-10, which has a thermal resistance (junction to ambient) of

RθJA = 60°C/W.

Figure 6.1

ZLED7015 Pin Configuration—MSOP-10 Package

Table 6.1

Pin Description MSOP-10

Pin Name

No.

Description

PGND

1

Power ground

VP

2

Internal 5V linear regulator output. VP is the power supply for the internal switch gate driver and the

internal control circuitry. Use a 10µF ceramic bypass capacitor between VP and ground.

AGND

3

Analog (signal) ground.

EN

4

Enable control input. Important: Do not allow this pin to float.

AGND

5

Analog (signal) ground.

OVP

6

Over-voltage protection control input.

FB

7

Feedback voltage input. The nominal average output current is set by the value of RS connected from

FB to GND – see section 2.2.1 for details. Important: Do not allow the FB pin to float.

n.c.

8

No connection

VDD

9

Supply voltage (6V to 30V)—see section 7 for layout considerations.

LX

10

Drain of the internal switch. Connect the power inductor between LX and the power supply. Connect the

output rectifier D1 between LX and the output circuit. See section1.1 for output range specifications.

Thermal

Pad

Connect to ground.