HC705C9AGRSSLASHD datasheet(21/157 Pages) NXP

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General Release Specification

Configuration Options

MC68HC705C9A — Rev. 2.0

General Description

•

SPI output signals (MOSI, MISO, and SCK) require the

corresponding bits in the port D data direction register to be set for

output.

•

The port D wire-OR mode control bit (bit 5 of SPCR $000A) is

enabled, allowing open-drain configuration of port D.

•

The RESET pin becomes bidirectional; this pin is driven low by a

C9A COP or clock monitor timeout or during power-on reset.

When configured as an MC68HC05C12A:

•

Memory locations $0100–$0FFF are disabled, creating a memory

map identical to the MC68HC05C12A.

•

C12A options in the C12MOR ($3FF1) are enabled; these bits

control IRQ sensitivity, STOP instruction disable and C12 COP

enable.

•

The C9A option register ($3FDF) is disabled, preventing software

control over the IRQ sensitivity and the memory map

configuration.

•

The C9A COP reset register ($001D) and the C9A COP control

C9A COP and clock monitor.

•

The C12 COP clear register ($3FF0) is enabled; this write-only

•

The port D data direction register ($0007) is disabled and the

seven port D pins become input only.

•

SPI output signals (MOSI, MISO, and SCK) do not require the

data direction register control for output capability.

•

The port D wire-OR mode control bit (bit 5 of SPCR $000A) is

disabled, preventing open-drain configuration of port D.

•

The RESET pin becomes input only.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705C9AGRS/D 数据表(PDF) 21 Page - NXP Semiconductors

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