ISL70003SEHFSLASHPROTO datasheet(21/32 Pages) RENESAS

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ISL70003SEH

FN8604 Rev 6.00

Page 21 of 32

December 8, 2016

logic activates the power blocks, the regulator ramps the output

voltage to its set value within a soft-start interval, however, the

device no longer goes through the preinitialization phase.

Transitions between the number of active LXx pins through the

use of SEL1 and SEL2 should not be done while the part is

operating. On the fly transitions will cause glitches on the output

voltage, which may exceed transient requirements. It is

recommended to place the ISL70003SEH in Standby mode, by

pulling SEL1 and SEL2 HIGH, and then change the number of

active LXx pins.

The overcurrent trip point scales depending on the number of

active power blocks. Equation 10 may be used to determine the

value of ROCSETA and ROCSETB when less than 10 power blocks

are active:

where N is the number of active phases.

IMON Current-Sense Output

The ISL70003SEH provides a current monitor function through

IMON. Current monitoring informs designers if downstream loads

are operating as expected. It is also useful in the prototype and

debug phase of the design and during normal operation to

measure the overall performance of a system. The IMON pin

outputs a high-speed analog current source that is proportional

to the sensed peak current through the ISL70003SEH. In typical

applications, a resistor, RIMON, is connected to the IMON pin to

convert the sensed current to voltage, VIMON, which is

proportional to the peak current, as shown in Equation 11:

where VIMON is the voltage at the IMON pin, RIMON is the resistor

between the IMON pin and AGND, ISAMPLE is the current through

the converter at the time IMON samples the current, and N is the

number of active power blocks. ISAMPLE may be calculated from

Equation 12.

where tSAMPLE is the time it takes the IMON circuitry to sample

the current (300ns, max), ILOAD is the load current and ΔI is the

inductor peak-to-peak ripple current as calculated in Equation 7.

A small capacitor should be placed between the IMON pin and

AGND to reduce the noise impact and mitigate single-event

transients. If this pin is not used, it is best connected to VREFA. It

is also acceptable to tie to GND through a resistor.

Figures 42 and 43 show the response of the IMON current

monitor due to a load step with a RIMON = 10kΩ and 100pF

ceramic capacitor in parallel.

It is important to note that if the on-time of the lower NMOS FET

is shorter than the IMON current-sense time (300ns max), the

IMON output is tri-stated after four consecutive failed sense

occurrences.

Diode Emulation

Diode Emulation (DE) allows for higher converter efficiency under

light-load situations. In DE mode, the low-side MOSFET conducts

when the current is flowing from source-to-drain and does not

allow reverse current, emulating a diode. As shown in Figure 44,

when the LGATE signal is HIGH, the low-side MOSFET carries

current, creating negative voltage on the phase node due to the

voltage drop across the ON-resistance. When the DE pin is pulled

HIGH, the ISL70003SEH will be in Diode Emulation mode and

detect the zero current crossing of the inductor current, and turn

off the lower MOSFET to prevent the inductor current from

reversing direction and creating unnecessary power loss. This

ensures that Discontinuous Conduction Mode (DCM) is achieved.

Since diode emulation prevents the low-side MOSFET from

sinking current, no negative spike at the output is generated

during prebiased startup when DE mode is active.

After a significantly fast load release transient, diode emulation

will not allow the converter to bring the output voltage back down

following the hump created by the inductor energy dump into the

output capacitor bank. The ISL70003SEH overcomes this issue

by monitoring the output of the error amplifier and allowing the

low-side MOSFET to turn on and sink the necessary current

ROCSET A B





3602.4 N



IOCP

-----------------------------

(EQ. 10)

VIMON

100 10

–



ISAMPLE RIMON



---------------------------------------------------



(EQ. 11)

ISAMPLE

ILOAD

I

-----

I

tSAMPLE fSW



–



------------------------------------------







–

(EQ. 12)

FIGURE 42. IMON RESPONSE TO 6A LOAD STEP

FIGURE 43. IMON RESPONSE TO 6A LOAD RELEASE

TIME (5µs/DIV)

VIMON VOLTAGE

200mV/DIV

INDUCTOR CURRENT 2A/DIV

INDUCTOR

2A/DIV

CURRENT

VIMON VOLTAGE

200mV/DIV

TIME (5µs/DIV)

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