ISL98607

4. Application Information

FN8421 Rev.1.00

Page 13 of 29

Jun.3.19

4.4

Register Descriptions and Addresses

Table 2 on page 15 contains the detailed register map, with descriptions and addresses for ISL98607 registers.

Each volatile register is one byte (8-bit) in size. When writing data to adjust register settings using I2C, the data is

latched-in after the 8th bit (LSB) is received.

The ISL98607 has default register settings that are always applied at IC power-ON or after a reset. In Table 2, the

default register settings are indicated with Bold face text.

Reserved registers should only be written with the bit value indicated in the Register Map. Also, Register

Addresses (pointers) not indicated in the Register Map are reserved and should not be written to.

Note: To clear/reset all the volatile registers to the default values, power cycle VIN.

4.5

Register Functions

The ISL98607 has various registers that can be used to adjust and control IC operating voltages, modes,

thresholds, and sequences.

4.5.1 ENABLE

The “ENABLE” register (Register Address 0x05) controls the enable/disable state of the boost (VBST), positive

LDO (VP), and negative charge pump (VN) regulators, which sequences the regulators.

4.5.2 VBST_OUT, VN_OUT, VP_OUT

The output voltages of VBST, VP, and VN regulators are changed using the registers VBST_OUT (Register

Address 0x06), VP_OUT (Register Address 0x09), and VN_OUT (Register Address 0x08), respectively.

The output voltages of all three regulators are changed from their default values using I2C. The VP regulator is

programmed from +5V to +5.7V, the VN regulator is programmed from -5V to -5.7V, and the VBST regulator is

programmed from +5.15V to +6.0V (each adjustable with 50mV step size). Do not use register settings that result

in an expected output voltage above these maximum levels. To determine the expected output voltage for a

specific register value, see “Output Voltage Calculation” on page 14.

Note: The output voltage registers should not be changed during their respective soft-start sequence.

Figure 16. I2C Read Timing Diagram

Write

Register

Pointer

SDA

(from Master)

SDA

(from Slave)

SCL

(from Master)

76 543 2 1 0

A

765 432 10

A

A

765 432 10 A

Read Data

SDA

(from Master)

SDA

(from Slave)

SCL

(from Master)

76 543 2 1 0 A

START

Device Address R

Start

Device Address W

Register Pointer

Stop

NOTE: First send register pointer to

indicate the read-back starting location

A

This Stop condition is optional (not

required) to do read-back. The device

also supports repeated starts.

76 543 210 A

(No ACK)

Data

Stop

76 543 210

A

7 6 5 432 10

Device Address = 0x29

A

76 543 2 1 0

Device Address = 0x29