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DSP56001A

Synchronous Serial Interface (SSI) Timing

MOTOROLA

DSP56001A/D, Rev. 1

2-21

SYNCHRONOUS SERIAL INTERFACE (SSI) TIMING

VCC = 5.0 V ± 10% for 27 MHz; VCC = 5.0 V ± 5% for 33 MHz;

TJ = –40 to 105˚ C; CL = 50 pF + 2 TTL loads

tSSICC = SSI clock cycle time

TXC (SCK Pin) = Transmit Clock

RXC (SC0 or SCK Pin) = Receive Clock

FST (SC2 Pin) = Transmit Frame Sync

FSR (SC1 or SC2 Pin) = Receive Frame Sync

i ck = Internal Clock

x ck = External Clock

g ck = Gated Clock

i ck a = Internal Clock, Asynchronous mode (Asynchronous implies that

STD and SRD are two different clocks)

i ck s = Internal Clock, Synchronous mode (Synchronous implies that

STD and SRD are the same clock)

bl =

bit length

wl =

word length

Table 2-12

SSI Timing

Num

Characteristics

27 MHz

33 MHz

Case

Unit

Min

Max

Min

Max

Clock Cycle—tSSICC (See

Note 1)

× T

—4

× T

——

Clock High Period

× T

C – 15

—

× T

C – 13

—

Clock Low Period

× T

C – 15

—

× T

C – 13

—

SRD Rising Edge to FSR

Out (bl) High

—

x ck

i ck a

SRD Rising Edge to FSR

Out (bl) Low

—

xck

i ck a

SRD Rising Edge to FSR

Out (wl) High

—

x ck

i ck a

RXC Rising Edge to FSR

Out (wl) Low

—

x ck

i ck a

Data In Setup Time

Before RXC (SCK in

Synchronous Mode)

Falling Edge

—

x ck

i ck a

i ck s

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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