ADIS16006SLASHPCB datasheet(4/16 Pages) AD

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ADIS16006

Rev. 0 | Page 4 of 16

Conditions

Min

Typ

Max

Unit

Parameter

POWER SUPPLY

Operating Voltage Range

3.0

5.25

Quiescent Supply Current

FSCLK = 50 kSPS

1.5

1.9

Power-Down Current

1.0

Turn-On Time6

CX, CY = 0.1 μF

1 Guaranteed by measurement of initial offset and sensitivity.

2 Defined as the output change from ambient to maximum temperature or ambient to minimum temperature.

3 Actual bandwidth response controlled by user-supplied external capacitor (CX, CY).

4 See the Setting the Bandwidth section for more information on how to reduce the bandwidth.

5 Self-test response changes as the square of VCC.

6 Larger values of CX and CY increase turn-on time. Turn-on time is approximately (160 × (0.0022 + CX or CY) + 4) in milliseconds, where CX and CY are in μF.

TIMING CHARACTERISTICS

TA = −40°C to +125°C, acceleration = 0 g, unless otherwise noted.

Table 2.

Parameter1, 2

VCC = 3.3 V

VCC = 5 V

Unit

Description

fSCLK3

kHz min

MHz max

tCONVERT

14.5 × tSCLK

tACQ

1.5 × tSCLK

Throughput time = tCONVERT + tACQ = 16 × tSCLK

ns min

TCS/CS to SCLK setup time

ns max

Delay from TCS/CS until DOUT three-state disabled

t24

t34

100

ns max

Data access time after SCLK falling edge

ns min

Data setup time prior to SCLK rising edge

ns min

Data hold time after SCLK rising edge

0.4 × tSCLK

ns min

SCLK high pulse width

0.4 × tSCLK

ns min

SCLK low pulse width

ns max

TCS/CS rising edge to DOUT high impedance

t85

μs typ

Power-up time from shutdown

1 Guaranteed by design. All input signals are specified with tR and tF = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.6 V. The 3.3 V operating range spans

from 3.0 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V.

2 See Figure 3 and Figure 4.

3 Mark/space ratio for the SCLK input is 40/60 to 60/40.

4 Measured with the load circuit in Figure 2 and defined as the time required for the output to cross 0.4 V or 2.0 V with VCC = 3.3 V and time for an output to cross 0.8 V or

2.4 V with VCC = 5.0 V.

5 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated

back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the Timing Characteristics is the true bus relinquish

time of the part and is independent of the bus loading.

CIRCUIT AND TIMING DIAGRAMS

200µA

IOL

200µA

IOH

1.6V

TO OUTPUT

50pF

Figure 2. Load Circuit for Digital Output Timing Specifications

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