Data Sheet
SC-605
© 2002 Sensory Inc.
P/N 80-0209-A
3
Pin/Pad Assignment
SC-605
(top view of the die)
19
20
32
33
52
1
SC-605
(100-lead TQFP)
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
75
74
73
72
71
70
69
68
67
66
65
60
59
58
57
56
NC
NC
NC
55
54
53
NC
64
NC
NC
NC
63
62
61
NC
52
NC
51
NC
NC
NC
NC
DACM
VDD
DAVP
VDD
PF7
PF6
PF5
PF4
NC
1
2
3
4
5
6
7
8
9
10
11
12
20
PF3
PF2
PF1
PF0
VSS
NC
NC
13
14
15
16
17
18
19
NC
NC
NC
NC
NC
21
22
23
24
25
NAME
PIN NO.
PAD NO.
I/O DESCRIPTION
Input/Output Ports
PC0 – PC7
89 → 82
8 → 1
I/O Port C general-purpose I/O (1 Byte)
PD0 – PD7
99 → 92
18 → 11
I/O Port D general-purpose I/O (1 Byte)
PE0 – PE7
46 → 39
48 → 41
I/O Port E general-purpose I/O (1 Byte)
PF0 – PF7
16 → 9
31 → 24
I
Port F key-scan input (1 Byte)
Pins PD4 and PD5 may be dedicated to the comparator function, if the comparator enable bit is set.
Scan Port Control Signals
SCANIN
37
39
I
Scan port data input
SCANOUT
33
35
O Scan port data output
SCANCLK
36
38
I
Scan port clock
SYNC
35
37
I
Scan port synchronization
TEST
34
36
I
C605: test modes
The scan port pins must be bonded out on any SC-605 production board.
Reference Oscillator Signals
OSCOUT
49
51
O Resistor/crystal reference out
OSCIN
48
50
I
Resistor/crystal reference in
PLL
47
49
O Phase-lock-loop filter
Digital-to-Analog Sound Output
DACP
7
22
O Digital-to-analog plus output (+)
DACM
5
20
O Digital-to-analog minus output (–)
Initialization
RESET
38
40
I
Initialization
Power Signals
VSS
17, 50, 90, 100
†
32, 52, 9, 19
†
-
Ground
VDD
6
†, 8, 31, 32, 91 21†, 23, 33, 34, 10 - Processor power (+)
† The VSS and VDD connections service the DAC circuitry. Their pins tend to sustain a higher current draw. A dedicated decoupling capacitor
across these pins is therefore required.
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