ADIS16201SLASHPCB datasheet(5/32 Pages) AD

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Data Sheet

ADIS16201

Rev. C | Page 5 of 32

TIMING SPECIFICATIONS

TA = 25°C, VDD = 3.3 V, tilt = 0°, unless otherwise noted.

Table 2.

Parameter

Description

Min1

Typ

Max

Unit

fSCLK

Fast mode, SMPL_TIME ≤ 0x07 (fs ≥ 1024 Hz)

0.01

2.5

MHz

Normal mode, SMPL_TIME ≥ 0x08 (fs ≤ 910 Hz)

0.01

1.0

MHz

tDATARATE

Chip select period, fast mode, SMPL_TIME ≤ 0x07 (fs ≥ 1024 Hz)

μs

tDATARATE

Chip select period, normal mode, SMPL_TIME ≥ 0x08 (fs ≤ 910 Hz)

μs

tSTALL

Stall period, fast mode, SMPL_PRD ≤ 0x07 (fs ≥ 1024 Hz)

μs

tSTALL

Stall period, normal mode, SMPL_PRD ≥ 0x08 (fs ≤ 910 Hz)

μs

tcs

Chip select to clock edge

48.8

tDAV

Data output valid after SCLK edge

100

tDSU

Data input setup time before SCLK rising edge

24.4

tDHD

Data input hold time after SCLK rising edge

48.8

tDF

Data output fall time

12.5

ns min

tDR

Data output rise time

12.5

ns min

tSFS

CS high after SCLK edge

ns typ

1 Guaranteed by design, not tested.

TIMING DIAGRAMS

SCLK

tDATA RATE

tSTALL = tDATA RATE – 16/fSCLK

tSTALL

Figure 2. SPI Chip Select Timing

SCLK

DOUT

DIN

W/R

MSB

DB14

LSB

DB13

DB12

DB10

DB11

DB2

LSB

DB1

tCS

tSFS

tDAV

tDHD

tDSU

Figure 3. SPI Timing

(Utilizing SPI Settings Typically Identified as Phase = 1, Polarity = 1)

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