ADM1175

Rev. 0 | Page 19 of 24

WRITE EXTENDED BYTE

In the write extended byte operation, the master device writes

to one of the three extended registers of the slave device, as follows:

1.

The master device asserts a start condition on SDA.

2.

The master sends the 7-bit slave address, followed by the

write bit (low).

3.

The addressed slave device asserts an acknowledge on SDA.

4.

The master sends the register address byte. The MSB of

this byte is set to 1 to indicate an extended register write.

The two LSBs indicate which of the three extended

registers are to be written to (see Table 8). All other bits

should be set to 0.

5.

The slave asserts an acknowledge on SDA.

6.

The master sends the command byte. The command byte

is identified by an MSB = 0. An MSB = 1 indicates an

extended register write.

7.

The slave asserts an acknowledge on SDA.

8.

The master asserts a stop condition on SDA to end the

transaction.

S

SLAVE

ADDRESS

WA

REGISTER

ADDRESS

AP

REGISTER

DATA

A

12

3

4

5

6

7 8

Figure 37. Write Extended Byte

Table 9, Table 10, and Table 11 give details of each extended

register.

Table 8. Extended Register Addresses

A6

A5

A4

A3

A2

A1

A0

Extended Register

0

0

0

0

0

0

1

ALERT_EN

0

0

0

0

0

1

0

ALERT_TH

0

0

0

0

0

1

1

CONTROL

Table 9. ALERT_EN Register Operations

Bit

Default

Name

Function

0

0

EN_ADC_OC1

Enabled if a single ADC conversion on the I channel has exceeded the threshold set in the ALERT_TH

register.

1

0

EN_ADC_OC4

Enabled if four consecutive ADC conversions on the I channel have exceeded the threshold set in the

ALERT_TH register.

2

1

EN_HS_ALERT

Enabled if the hot swap has either latched off or entered a cool-down cycle because of an overcurrent

event.

3

0

EN_OFF_ALERT

Enables an alert if the HS operation is turned off by a transition that deasserts the ON/ONB pin or by an

operation that writes the SWOFF bit high.

4

0

CLEAR

Clears the ON_ALERT, HS_ALERT and ADC_ALERT status bits in the STATUS register. These can

immediately reset if the source of the alert has not been cleared or disabled with the other bits in this

register. This bit self-clears to 0 after the STATUS register bits have been cleared.

Table 10. ALERT_TH Register Operations

Bit

Default

Function

7:0

FF

The ALERT_TH register sets the current level at which an alert occurs. Defaults to ADC full scale. The ALERT_TH 8-bit

number corresponds to the top eight bits of the current channel data.

Table 11. CONTROL Register Operations

Bit

Default

Name

Function

0

0

SWOFF

Forces hot swap off. Equivalent to deasserting the ON/ONB pin.