CS3155 datasheet(1/2 Pages) AMCC

部件名	CS3155

功能描述	SONET/SDH/ATM OC-48 Transceiver With CDR

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制造商	AMCC [Applied Micro Circuits Corporation]

网页	http://www.amcc.com

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A t a Glan ce

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Product Brief

S3155

SONET/SDH/ATM OC-48 Transceiver With CDR

Empowering Intelligent Optical Networks

1

PB1135_v1.01_05/09/03

Description

The S3155 SONET/SDH transceiver

chip is a fully integrated serialization/

deserialization SONET OC-48 (2.488 -

2.67 Gbps) interface device. The S3155

receives an OC-48 scrambled Non-

Return to Zero (NRZ) signal and

recovers the clock from the data. The

chip performs all necessary serial-to-

parallel and parallel-to-serial functions in

conformance with SONET/SDH

transmission standards. The device is

suitable for SONET-based WDM

applications. The figure below shows a

typical network application.

On-chip clock synthesis is performed by

the high-frequency Phase-Locked Loop

(PLL) on the S3155 transceiver chip

allowing the use of a slower external

transmit clock reference. The chip can

be used with a 155.52 or 166.63 MHz

reference clock in support of existing

system clocking schemes.

The low jitter LVPECL interface is

compliant with the bit-error rate

requirements of the Telecodia and ITU-T

standards. The S3155 is packaged in a

196 PBGA, offering designers a small

package outline.

Overview

The S3155 transceiver implements

SONET/SDH serialization/deserializa-

tion, and transmission functions. This

chip canbe usedtoimplement the front

end of SONET equipment, which con-

sists primarily of the serial transmit inter-

face and the serial receive interface. The

chip handles all the functions of these

two elements, including parallel-to-serial

and serial-to-parallel conversion, clock

generation, and system timing. The

S3155 is divided into a transmitter sec-

tion and a receiver section. The

sequence of operations is as follows:

Transmitter Operations:

1.

16-bit parallel input

2.

Parallel-to-serial conversion

3.

Serial output

Receiver Operations:

1.

Clock and data recovery from serial

input

2.

Serial-to-parallel conversion

3.

16-bit parallel output

Features

•

650 mW typical power

•

Integrated clock data recovery

•

On-chip high-frequency PLL

for clock generation and clock

recovery

•

Supports OC-48 (2.488 Gbps)

with FEC

•

Reference frequency of 155.52

to 166.63 MHz

•

RX and TX reference selectable

•

Interface to LVCMOS/LVTTL

logic

•

Internal input termination

option built-in

•

16-bit differential LVPECL/

LVDS data path or single-

ended LVPECL option

•

196 PBGA package

•

Diagnostic and line loopback

mode

•

Support serial loop timing

mode

•

Lock detect

•

Signal detect input with polarity

select

•

Low Jitter LVPECL/LVDS

interface

•

Internal FIFO to decouple

transmit clocks

Figure 1. System Block Diagram

16

S3155

ORX

OTX

ORX

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