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CS3157 数据表(PDF) 1 Page - Applied Micro Circuits Corporation |
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CS3157 数据表(HTML) 1 Page - Applied Micro Circuits Corporation |
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1 / 2 page  – At a G l a n c e – Product Brief S3157 GPON Transceiver With CDR Empowering Intelligent Optical Networks 1 PB2023_v1.00_08/25/05 Description The S3157 GPON transceiver chip is a fully integrated serialization/ deserialization GPON OC-48/24/12 transceiver interface device. The S3157 receives an OC-48/24/12 Non-Return to Zero (NRZ) signal and recovers the clock from the data. The chip performs all necessary serial-to-parallel and parallel-to-serial functions in conformance with GPON transmission standards. The device is suitable for GPON-based applications. The figure below shows a typical network application. On-chip clock synthesis is performed by the high-frequency Phase-Locked Loop (PLL) on the S3157 transceiver chip allowing the use of a slower external transmit clock reference. The chip can be used with a 155.52 or 166.63 MHz reference clock in support of existing system clocking schemes. The low jitter LVPECL interface is compliant with the bit-error rate requirements of the ITU-T standards. The S3157 is packaged in a 196 PBGA, offering designers a small package outline. Overview The S3157 transceiver implements GPON serialization/deserialization, and transmission functions. This chip can be used to implement the front end of GPON equipment, which consists primarily of the serial transmit interface and the serial receive interface. The chip handles all the functions of these two elements, including parallel-to-serial and serial-to-parallel conversion, clock generation, and system timing. The S3157 is divided into a transmitter section and a receiver section. The sequence of operations is as follows: Transmitter Operations: 1. 16-bit parallel input 2. Parallel-to-serial conversion 3. Serial output Receiver Operations: 1. Clock and data recovery from serial input 2. Serial-to-parallel conversion 3. 16-bit parallel output Due to the asynchronous nature of the GPON, the FPGA that connects to the S3157 has to accommodate for the 1/2 upstream data rate. Features • 650 mW typical power • Integrated clock data recovery • On-chip high-frequency PLL for clock generation and clock recovery • Supports OC-48/24/12 rates • Reference frequency of 155.52 to 166.63 MHz • RX and TX reference selectable • Interface to LVCMOS/LVTTL logic • Internal input termination option built-in • 16-bit differential LVPECL/ LVDS data path or single- ended LVPECL option • 196 PBGA package • Diagnostic and line loopback mode • Support serial loop timing mode • Lock detect • Signal detect input with polarity select • Low Jitter LVPECL/LVDS inter- face • Internal FIFO to decouple transmit clocks Continued on next page... Figure 1. System Block Diagram TX: ½ Rate Adaptation FPGA RX: 2.5 G, 1.25 G or 622 Mbps FPGA 16 AMCC S3157 16 ½ AMCC S3157 OLT 16 ½ AMCC S2060 Optical Mux PON Splitter E/O O/E CATV 1.25 Gbps 622 Mbps 155 Mbps 2.5 Gbps 1.25 Gbps 622 Mbps 16 ONU |
类似零件编号 - CS3157 |
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类似说明 - CS3157 |
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