ICS9DB823B

EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1, GEN2 AND QPI

IDT®

EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1, GEN2 AND QPI

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ICS9DB823B

REV F 091812

Revision History

Rev.

Issue Date Description

Page #

A

10/1/2008

1. Updated Electrical Characteristics to add propagation delay and

phase noise information.

2. Added SMBus electrical characteristics

3. Added foot note about DIF input running in order for the SMBus

interface to work

4. Added foot note to Byte 1 about functionality of OE bits and OE pins

5. Updated clock periods to reflect +/-100ppm input clock tolerance

(CK410B+/CK420BQ/CK505).

6. Changed SRC_Stop references to DIF_Stop references for

consistency..

Various

B

10/7/2008

Corrected Common Dimensions.

19-20

C

2/4/2010

1. Corrected Polarity of Power Down pin when OE_INV = 1. Power

Down is always active low (or PD#). This is a difference from the

9DB803D.

Various

D

8/31/2010

1. Corrected Termination drawings/tables

2. Removed "Polarity Inversion Pin List" table.

Various

E

5/9/2011

1. Update pin 2 pin-name and pin description from VDD to VDDR. This

highlights that optimal peformance is obtained by treating VDDR as in

analog pin. This is a document update only, there is no silicon change.

Various

F

9/18/2012

Updated Byte 2, bits 0~7 per char review. Outputs can be programmed

with Byte 2 to be Stoppable or Free-Run with DIF_Stop pin, not the OE

pins.

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