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ICS9LPRS355 数据表(PDF) 21 Page - Renesas Technology Corp |
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ICS9LPRS355 数据表(HTML) 21 Page - Renesas Technology Corp |
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21 / 28 page  21 ICS9LPRS355 Datasheet 1205—06/24/14 Byte 9 Output Control Register Bit Pin Name Description Type 0 1 Default 7 PCIF5 STOP EN Allows control of PCIF5 with assertion of PCI_STOP# RW Free running Stops with PCI_STOP# assertion 0 6 TME_Readback Truested Mode Enable (TME) strap status R normal operation no overclocking 0 5 REF Strength Sets the REF output drive strength RW 1X (2Loads) 2X (3 Loads) 1 4 Test Mode Select Allows test select, ignores REF/FSC/TestSel RW Outputs HI-Z Outputs = REF/N 0 3 Test Mode Entry Allows entry into test mode, ignores FSB/TestMode RW Normal operation Test mode 0 2 IO_VOUT2 IO Output Voltage Select (Most Significant Bit) RW 1 1 IO_VOUT1 IO Output Voltage Select RW 0 0 IO_VOUT0 IO Output Voltage Select (Least Significant Bit) RW 1 Byte 10 Free-Running Control Register Bit Pin Name Description Type 0 1 Default 7 27_Selec Latch read back Readback of 27_Select latch R Dot96/ LCD_SS /SE SRC0/ 27MHz 27_Select latch 6 Reserved Reserved RW -- 1 5 Reserved Reserved RW -- 1 4 CPU1_AMT_EN* M1 mode clk enable RW Disable Enable 1 3 Reserved Reserved RW -- 1 2 CPU 2 Stop Enable* Enables control of CPU2 with CPU_STOP# RW Free Running Stoppable 1 1 CPU 1 Stop Enable Enables control of CPU1 with CPU_STOP# RW Free Running Stoppable 1 0 CPU 0 Stop Enable Enables control of CPU 0 with CPU_STOP# RW Free Running Stoppable 1 *9LPRS355C Only Byte 11 Strength Control Register Bit Pin Name Description Type 0 1 Default 7 48MHz RW 1x 2x 0 6 PCIF5 RW 1x 2x 0 5PCI4 RW 1x 2x 0 4PCI3 RW 1x 2x 0 3PCI2 RW 1x 2x 0 2PCI1 RW 1x 2x 0 1PCI0 RW 1x 2x 0 0 Reserved RW 0 Byte 12 Byte Count Register Bit Pin Name Description Type 0 1 Default 7 Reserved RW 0 6 Reserved RW 0 5BC5 RW 0 4BC4 RW 0 3BC3 RW 1 2BC2 RW 1 1BC1 RW 0 0BC0 RW 1 Byte 13 VCO Frequency Control Register PLL1 Bit Pin Name Description Type 0 1 Default 7 N Div8 N Divider 8 RW - - X 6 N Div9 N Divider 9 RW - - X 5 M Div5 RW - - X 4 M Div4 RW - - X 3 M Div3 RW - - X 2 M Div2 RW - - X 1 M Div1 RW - - X 0 M Div0 RW - - X See Table 3: V_IO Selection (Default is 0.8V) Read Back byte count register, max bytes = 32 The decimal representation of M Div (5:0) is equal to reference divider value. Default at power up = latch-in or Byte 0 Rom table. Strength control |
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