IDTTM/ICSTM

64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor

1121G—05/19/11

Advance Information

ICS9LPRS501

64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR

13

Electrical Characteristics - Input/Supply/Common Output DC Parameters

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Notes

Ambient Operating Temp

Tambient

-

0

25

70

°C

Supply Voltage

VDDxxx

Supply Voltage

3.135

3.3

3.465

V

Supply Voltage

VDDxxx_IO

Low-Voltage Differential I/O Supply

0.9975

1.05

3.465

V

10

Input High Voltage

VIHSE

Single-ended 3.3V inputs

2.2

VDD + 0.3

V

3

Input Low Voltage

VILSE

Single-ended 3.3V inputs

VSS - 0.3

0.8

V

3

Low Threshold Input-

High Voltage FSC = Test Mode

VIH_FSC_TEST

3.3 V +/-5%

2

V

8

Low Threshold Input-

FSC = '1' Voltage

VIH_FSC_1

3.3 V +/-5%

0.7

1.5

V

8

Low Threshold Input-

FSA,FSB = '1' Voltage

VIH_FSAB_1

3.3 V +/-5%

0.7

V

Low Threshold Input-

Low Voltage

VIL_FS

3.3 V +/-5%

VSS - 0.3

0.35

V

Input Leakage Current

IIN

VIN = VDD , VIN = GND

-5

5

uA

2

Input Leakage Current

IINRES

Inputs with pull up or pull down resistors

VIN = VDD , VIN = GND

-200

200

uA

Output High Voltage

VOHSE

Single-ended outputs, IOH = -1mA

2.4

V

Output Low Voltage

VOLSE

Single-ended outputs, IOL = 1 mA

0.4

V

IDDOP3.3

Full Active, CL = Full load; IDD 3.3V

135

200

mA

IDDOPIO

Full Active, CL = Full load; IDD IO

72

80

mA

IDDiAMT3.3

M1 mode, 3.3V Rail

53

65

mA

IDDiAMTIO

M1 Mode, IO Rail

7

10

mA

IDDPD3.3

Power down mode, 3.3V Rail, B63b0 = '1'

22

25

mA

IDDPDIO

Power down mode, IO Rail

0.01

0.1

mA

Input Frequency

Fi

VDD = 3.3 V

14.31818

15

MHz

Pin Inductance

Lpin

7nH

CIN

Logic Inputs

1.5

5

pF

COUT

Output pin capacitance

6

pF

CINX

X1 & X2 pins

6

pF

Clk Stabilization

TSTAB

From VDD Power-Up or de-assertion of PD to

1st clock

1.2

1.8

ms

Tdrive_CR_off

TDRCROFF

Output stop after CR deasserted

400

ns

Tdrive_CR_on

TDRCRON

Output run after CR asserted

0

us

Tdrive_CPU

TDRSRC

CPU output enable after

PCI_STOP# de-assertion

10

ns

Tfall_SE

TFALL

10

ns

1

Trise_SE

TRISE

10

ns

1

SMBus Voltage

VDD

2.7

5.5

V

Low-level Output Voltage

VOLSMB

@ IPULLUP

0.4

V

Current sinking at

VOLSMB = 0.4 V

IPULLUP

SMB Data Pin

4

mA

SCLK/SDATA

Clock/Data Rise Time

TRI2C

(Max VIL - 0.15) to

(Min VIH + 0.15)

1000

ns

SCLK/SDATA

Clock/Data Fall Time

TFI2C

(Min VIH + 0.15) to

(Max VIL - 0.15)

300

ns

Maximum SMBus Operating Frequency

FSMBUS

100

kHz

Spread Spectrum Modulation

Frequency

fSSMOD

Triangular Modulation

30

32.54

33

kHz

NOTES on DC Parameters: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).

1Signal is required to be monotonic in this region.

2 input leakage current does not include inputs with pull-up or pull-down resistors

3 3.3V referenced inputs are: PCI_STOP#, CPU_STOP#, TME, SRC5_EN, ITP_EN, SCLKL, SDATA, TESTMODE, TESTSEL, CKPWRGD and CR# inputs if selected.

4 Intentionally blank

Powerdown Current

Input Capacitance

Fall/rise time of all 3.3V control inputs from 20-

80%. Inputs must be monotonic

Operating Supply Current

iAMT Mode Current