IDTTM/ICSTM

DDR I/DDR II Phase Lock Loop Zero Delay Buffer

ICS9P935

REV H

12/1/08

ICS9P935

DDR I/DDR II Phase Lock Loop Zero Delay Buffer

12

Ordering Information

ICS9P935yGLF-T

Example:

Designation for tape and reel packaging

RoHS Compliant (Optional)

Package Type

G = TSSOP

Revision Designator (will not correlate with datasheet revision)

Device Type

Prefix

ICS = Standard Device

ICS XXXX y G LF- T

MIN

MAX

MIN

MAX

A

--

1.20

--

.047

A1

0.05

0.15

.002

.006

A2

0.80

1.05

.032

.041

b

0.19

0.30

.007

.012

c

0.09

0.20

.0035

.008

D

E

E1

4.30

4.50

.169

.177

e

L

0.45

0.75

.018

.030

N

α

0°

8°

0°

8°

aaa

--

0.10

--

.004

VARIATIONS

MIN

MAX

MIN

MAX

28

9.60

9.80

.378

.386

10-0035

SEE VARIATIONS

SEE VARIATIONS

0.65 BASIC

Reference Doc.: JEDEC Publication 95, MO-153

N

SEE VARIATIONS

SEE VARIATIONS

D mm.

D (inch)

4.40 mm. Body, 0.65 mm. Pitch TSSOP

6.40 BASIC

0.252 BASIC

0.0256 BASIC

COMMON DIMENSIONS

In Millimeters

In Inches

COMMON DIMENSIONS

(173 mil)

(25.6 mil)

SYMBOL