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AD9397/PCB 数据表(PDF) 7 Page - Analog Devices

部件名 AD9397/PCB
功能描述  DVI Display Interface
PDF  28 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9397/PCB 数据表(HTML) 7 Page - Analog Devices

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AD9397
Rev. 0 | Page 7 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
2
GREEN 7
3
GREEN 6
4
GREEN 5
7
GREEN 2
6
GREEN 3
5
GREEN 4
1
GND
8
GREEN 1
9
GREEN 0
10
VDD
12
BLUE 7
13
BLUE 6
14
BLUE 5
15
BLUE 4
16
BLUE 3
17
BLUE 2
18
BLUE 1
19
BLUE 0
20
NC
21
NC
22
NC
23
NC
24
CTL3
25
CTL2
11
GND
74
NC
GND
73
NC
72
VD
69
GND
70
NC
71
NC
75
68
NC
67
VD
66
NC
64
NC
63
NC
62
NC
61
NC
60
NC
59
PVDD
58
GND
57
NC
56
PVDD
55
GND
54
PVDD
53
GND
52
MDA
51
MCL
65
GND
PIN 1
AD9397
TOP VIEW
(Not to Scale)
NC = NO CONNECT
Figure 2. Pin Configuration
Table 5. Complete Pinout List
Pin Type
Pin No.
Mnemonic
Function
Value
INPUTS
81
PWRDN
Power-Down Control
3.3 V CMOS
DIGITAL VIDEO DATA INPUTS
35
Rx0+
Digital Input Channel 0 True
TMDS
34
Rx0−
Digital Input Channel 0 Complement
TMDS
38
Rx1+
Digital Input Channel 1 True
TMDS
37
Rx1−
Digital Input Channel 1 Complement
TMDS
41
Rx2+
Digital Input Channel 2 True
TMDS
40
Rx2−
Digital Input Channel 2 Complement
TMDS
DIGITAL VIDEO CLOCK INPUTS
43
RxC+
Digital Data Clock True
TMDS
44
RxC−
Digital Data Clock Complement
TMDS
OUTPUTS
92 to 99
RED [7:0]
Outputs of Red Converter, Bit 7 is MSB
VDD
2 to 9
GREEN [7:0]
Outputs of Green Converter, Bit 7 is MSB
VDD
12 to 19
BLUE [7:0]
Outputs of Blue Converter, Bit 7 is MSB
VDD
89
DATACK
Data Output Clock
VDD
87
HSOUT
HSYNC Output Clock (Phase-Aligned with DATACK)
VDD
85
VSOUT
VSYNC Output Clock (Phase-Aligned with DATACK)
VDD
84
O/E FIELD
Odd/Even Field Output
VDD
27, 26, 25, 24
CTL(0 to 3)
Control 0, 1, 2, 3
VDD



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